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Issue 5



Welcome to Issue 5 of the Cadence NewsLink
We hope you find this digest of news and other recently published information to be a useful resource and convenient way to keep up with what's new at Cadence.

Digital Implementation

• Cadence and GLOBALFOUNDRIES Announce Broad, Multi-Year Technology Agreement - Press Release
• Freescale Achieves Design Cycle Reduction and Superior Silicon Predictability with Cadence Model-Based Physical and Electrical DFM Solutions - Press Release
• Tilera Adopts Broad Range of Cadence Solutions for Multicore Processor Design - Press Release
• UMC Adopts Cadence 40-Nanometer Reference Flow for Low Power, Verification, Implementation and DFM-Aware Design - Press Release
• 5 Fascinating People I Met at the 2009 Design Automation Conference - Robert Dwyer Blog
• Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects - Kari Summers Blog
• Learn about Cadence tools, have some fun, and win a prize - Embedded.com
• See Cadence at the SoC Conference - Exhibit & Workshops
• Follow Cadence on Twitter
• Attend CDNLive! Silicon Valley 2009 Webinar Series; Choose from more than 60 technical webinars - Webinars
• Helping the electronics industry reap the benefits of Silicon-on-Insulator technology - SOI Design Clinic
  Resources:  Product Info  |  Community  |  Events & Webinars


Get Your Signals Straight at the First Annual Mixed-Signal Design Summit
Register now and join the growing mixed-signal solution community!

Power Forward Low-Power Design Summit
Enabling power-efficient design from system to silicon


Low-Power Solution



System Design and Verification

• Nethra Enlists Cadence Incisive Palladium Accelerator/Emulator To Speed Development of Advanced HD Image Processor - Press Release
• Cadence adds pieces to C-to-Silicon strategy - EDN
• Verification alive and well at SoC virtual conference - EETimes
• It is all about power analysis, exploration and tradeoffs - PDF Resource
  Resources:  Product Info  |  Community  |  Events & Webinars

Logic Design

• LG Electronics Adopts Cadence Conformal Technology for Improved Engineering Design Management, Faster Time to Market - Press Release
• VeriSilicon Delivers Chip Designs on Time and at Lower Cost with Cadence InCyte Chip Estimator - Press Release
• Minimize cost of test with Encounter DFT Architect - Product Info
• Achieve high-quality silicon with Encounter True-Time ATPG - Product Info
• Q&A Interview: Nimish Modi Describes Front End 'Paradigm Shift' - Richard Goering Blog
• The Current State of the Art for Physical Synthesis - A Response - Jeffrey Flieder Blog
• RTL Power Estimation - Jack Erickson Blog
• Attend CDNLive! Silicon Valley 2009 Webinar Series; Choose from more than 60 technical webinars - Webinars
• See Cadence at the International Test Conference - Event
• Follow Cadence on Twitter
  Resources:  Product Info  |  Community  |  Events & Webinars


  Logic Design Webinar Series
Technical presentations on various topics in logic design		  


Custom & RF Design

• Cadence Announces National Semiconductor Adoption of Virtuoso Simulation Solution for Complex Analog Designs - Press Release
• Toshiba Information Systems (Japan) Selects Cadence Mixed-Signal Design Solution - Press Release
• Cadence Mixed-Signal Solution: boost productivity, increase predictability, and ensure high-quality silicon - Solution Info
• LFoundry rolls RF process design kit aiming at designers of analog/mixed signal and RF devices - EE Times
• Blog series: Things You Didn't Know About Virtuoso - Stacy Whiteman Blogs
• RF Measurement Library: Capturing Circuit Characterization Setups on the Schematic - Alan Whittaker Blog
• Optimization Environment Enables Effective Reuse of Existing Design Modules - Hiroshi Ishikawa Blog
• Cadence End-to-end Design Solutions Enable UPEK to Consolidate Seamless Full-chip Design Flow - EDN Asia
• Toward a standard deep sub-micron analog design flow: Cadence enhances the Virtuoso Platform - EDN
• Archived webinar series: the Cadence Virtuoso platform - Archived Webinars (SourceLink login)
 Resources:  Product Info  |  Community  |  Events & Webinars


  DesignCon 2010
Call for Papers is now open		  


Functional Verification

• Self-Paced Demonstrations for Most popular Verification IP available on-line now! - Xuropa
• Want to significantly improve your verification methodology? Let Cadence help with the Verification Excellence Program - Product Support
• Want to jump start your utilization of OVM? Let Cadence help with the OVM Startup Service - Product Support
• Incisive Enterprise Simulator: Low-Power Verification at Warp Speed - Team genIES Blog
• FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364 - Adam Sherer Blog
• Looking for the latest information on the Open Verification Methodology -- OVM World has what you need including Community Contributions, Dowloads, OVM Books and much more! - OVM World
• Learn how to improve verification productivity using feature based coverage metrics - (SourceLink login)
• Important! The location of Incisive Verification Software Products Is Changing!
Look for the new "INCISIV" release on Cadence downloads starting with the October 9.2 version of Incisive verification software.
  Resources:  Product Info  |  Community  |  Events & Webinars

PCB Design & IC Packaging

• System-In-Package design technology included in TSMC Reference Flow 10.0 - Press Release
• Constraint-Driven HDI Design Flow Trims Nvidia's Design Cycle by 25% - Cadence Article
• Cadence Introduces Innovative FPGA-PCB Co-Design Solution - Cadence Article
• Introducing Cadence Allegro FPGA System Planner - Product Info
• Introducing Cadence OrCAD FPGA System Planner - Product Info
• Solving today's business-driven, complex design challenges - White Paper
• NEW Allegro PCB RF Option Datasheet - Datasheet
• Designing FPGA-Based Systems Successfully - White Paper
• What's Good About an FPGA Co-Design Environment? - Watch The Video For Answers - Gerald "Jerry" Grzenia Blog
• Everything You Want to Know About APD / SiP 16.2 - Brad Griffin Blog
• TSMC's 28-nm reference flow adds SiP solutions - EETimes
• Everything You Want to Know About APD / SiP 16.2 - Brad Griffin Blog
• If you happened to miss any of the 2009 webinars, it's not too late to request for any of the archived recordings. - Archived Webinars
 Resources:  Product Info  |  Community  |  Events & Webinars


  Allegro 2009 Summer Webinar Series
Register now to access the archived webinars! 		FPGA-PCB Co-Design Using Allegro/OrCAD FPGA System Planner
Register now for the archived webinar and to see a demo! 		 


Services, Support, Training

• Northrop Grumman Honors Cadence with Gold Supplier Award - Cadence Article
• Allegro PCB Editor Basics Technique - instructor-lead course - Training Info
• Allegro PCB Editor Basics Technique - self-paced course - Training Info
• Allegro PCB Editor Intermediate Technique - instructor-lead course - Training Info
• Allegro PCB Editor Intermediate Technique - self-paced course - Training Info
• Enhance your design framework knowledge and proficiency with the new IC 6.1.3 Virtuoso Design Environment course - Training Info
• Master floorplanning fundamentals and techniques with then new IC 6.1.3 Virtuoso Floorplanner Engineer Explorer course - Training Info
• SystemVerilog for Design - self-paced course - Training Info
• SystemVerilog for Verification - self-paced course - Training Info
• SystemVerilog Assertions - self-paced course - Training Info
• SystemVerilog Language and Application - instructor-lead course - Training Info
• SystemVerilog Advanced Verification using OVM - instructor-lead course - Training Info
• Core/ Basic Conformal - instructor-lead course - Training Info
• Advanced Conformal - instructor-lead course - Training Info
• Read more about how Cadence Global Services can help you stay ahead of the competition, manage the design and implementation of today's complex SOC's, and differentiate your products in the marketplace - Training Info
• Cadence Services Formally Addressing the SaaS Model - Pallab's Place
• Saving Time and Money with SaaS for EDA - EDA Thoughts
• Cadence Introduces New Functional Verification Packaged Services -- Learn More and Register for Webinar - Webinar
  Resources:  Services Info  |  Support & Training Info  |  Training Course Catalog

Alliances

• Cadence Achieves First-Silicon Results on 32nm Common Platform Technology - Press Release
• UMC Adopts Cadence 40-Nanometer Reference Flow for Low Power, Verification, Implementation and DFM-Aware Design - Press Release
• Cadence and GLOBALFOUNDRIES Announce Broad, Multi-Year Technology Agreement - Press Release
• GLOBALFOUNDRIES Enters Into Broad Technology Agreement with Cadence - Cadence Article
• Cadence collaborates with its foundry partners - Partner Info
• The Cadence IP Alliance Program enables interoperability and facilitates open collaboration with leading IP providers - Partner Info
• Real Low-Power Design--Really Fast! - Partner Info
• 32 nm Test Chips Show Layout 'Context' Matters - Richard Goering Blog
• User Interview: What to Expect At 32 nm and Below - Richard Goering Blog


  Cadence, ARM and Common Platform partners -- Chartered, IBM and Samsung -- have been working together to develop tools, design flows and IP capabilities for 32/28nm Common Platform technology.
Join us over breakfast in an in-depth discussion at the ARM Techcon3 Conference. 		 


 

Cadence Blogs
• Industry Insights
• System Design and Verification
• Functional Verification
• Logic Design
• Digital Implementation
• Custom IC Design
• RF Design
• PCB Design
• IC Packaging and SiP Design
• Manufacturability Signoff
• All Blogs

Industry Insights Blog
In our new Industry Insights blog, industry expert and respected journalist Richard Goering blogs on issues and technologies with an industry-wide perspective.
• Green Electronics -- Is SOI The Answer?
• Q&A Interview: Nimish Modi Describes Front End 'Paradigm Shift'
• DAC Report: Gary Smith's Prescription For 'Explosive' Growth
• Q&A Interview: Kurt Keutzer Charts Path To "Manycore" Parallelism
• User Interview: How STMicroelectronics Uses Virtual Platforms
• Intel vs ARM - Did the Embedded Systems Conference India Shed Light on the Battle?
• Full System vs Sub-system Virtual Prototyping
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