Power Forward Initiative - Summer 2007 Newsletter
Welcome to the summer edition of the PFI newsletter. May marked the 1 year anniversary of the formation of the Power Forward Initiative. We are proud of the Initiative's progress over the past year. Power Forward Advisors have worked diligently on proof point projects, prepared and delivered papers, and participated in industry events spreading the word on the benefits of CPF-based low power design. DAC provided opportunities for advisors to present their experiences using CPF-enabled low power design flows. In addition many companies in the ecosystem announced support for low power design flows based on CPF.

News
Ecosystem Support
In May, STARC completed an initial assessment of CPF using a test design and validated the value that CPF can provide. During H207, STARC will upgrade its PRIDE 3.0 flow to include CPF support and deliver it to their member companies.

At DAC, PFI founding member TSMC announced availability of TSMC Reference Flow 8.0, including holistic CPF support throughout each segment of the flow. The endorsement of CPF as the only power format supported in TSMC’s 8.0 reference flow establishes CPF’s leadership position in the industry.

Also at DAC, several members of the ecosystem announced their intent to support CPF in their tools in H207. LPC members Atrenta, ArchPro, Azuro, and ChipVision as well as Chipidea, Denali, Lightspeed Logic and Tensilica all joined the expanding list of EDA and IP suppliers who see the tremendous value of supporting CPF-based design flows.

Events Recap
Yokohama Low-power Design Workshop
On May 24th Cadence Japan hosted a sold out crowd of 109 customers for a day-long low power workshop. For the morning session, three Power Forward advisors were on hand to review their work within the initiative. Toshiyuki Saito from NEC Electronics highlighted his requirements for power logic verification and design productivity improvement and detailed their project to validate CPF flows using a 65nm design. Nobuyuki Nishiguchi, from STARC reviewed how their initial evaluation proved the advantage of the new methodology for power architecture exploration using multiple CPF files. Nishiguchi-san said they were better able to explore different architectures to reduce power while meeting timing specifications. Now they are developing a low-power reference flow using CPF. Satoru Yamaguchi from Fujitsu reviewed a recently taped out a design project using CPF and the Cadence Low-Power Solution. Based on their experience, they have decided to start using CPF to support their ASIC customers with a comprehensive low-power flow. Frank Childers, Si2 VP Business Operations, provided an update on the progress of CPF standardization in the Low-power Coalition whose membership include a broad cross-section of industry leaders. He highlighted that CPF 1.0 became a Si2 standard in Q1 2007 and is available to everyone in the industry from Si2 at no cost.

DAC
Si2 Sponsored CPF Workshop
On Sunday, Si2’s LPC organized a content packed workshop which included presentations by LPC members. Gill Watt from AMD and also Chairman of the LPC, gave an introduction to the Low Power Coalition, Qi Wang from Cadence gave an Overview of CPF, Gary Delp from LSI reviewed convergence activities with other Power-Aware Formats, Rob Aitken from ARM covered library considerations for low power, Herve Menager presented NXP’s end-user experiences, Jerry Frenkil from Sequence, Devadas Varma from Calypto, Dave Allen from Atrenta and Anand Iyer from ArchPro overviewed EDA Tool Developers Low Power perspectives. The presentations were followed by a lively panel discussion.

Cadence Low Power Panel
Cadence sponsored a lunchtime low power panel moderated by Chris Rowan, CEO Tensilica. He began the panel by stating that power is central to all design today, especially at advanced process nodes and addressing it at the systems level has the greatest impact. Devadas Varma continued on that theme and showed how system level optimizations can have a major impact on power consumption especially if those optimizations are carried forward into the implementation phase of the design with CPF. David Lan from TSMC who reviewed the just announced TSMC 8.0 reference flow that fully supports a cpf-enabled implementation flow. Nader Vasseghi of Cisco described why low power design at the systems level must be considered to minimize the “power” (consumption) of the internet. The 80+ attendees were treated to a very lively and engaging discussion and Q&A session by some of the most knowledgeable experts in the industry.

Low Power Solutions Seminar, Hsinchu, Taiwan
On August 22, Cadence co-sponsored another successful low power solutions seminar with FSA as part of FSA’s International Collaboration Series. The forum was attended by over 100 engineers from a broad range of Taiwan-based companies. The panelists discussed low power design challenges and how members of the design chain are coming together to meet those challenges. Pankaj Mayor of Cadence moderated the panel and overviewed Power Forward activities over the past year. Mickie Liu of ARM reviewed low power collaboration projects with Cadence as well as the upcoming CPF-enabled 1176 reference methodology. Pinhong Chen of Cadence reviewed Cadence low power solution, Albert Li of Global Unichip described how his design service company is addressing the low power challenges faced by their customers. Willy Chen from TSMC discussed the CPF-enabled TSMC Reference Flow 8.0.

Upcoming Events

Sequence – Design for Power Seminar
The Taj Residency
Bangalore, India
September 19, 2007
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Portable Design Conference
Santa Clara Convention Center
October 3, 2007
Active Power Management by Colin Holehouse, ARC International
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FSA Semiconductor Leaders Forum
Taipei International Convention Center, Taipei
November 7, 2007
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Sequence – Design for Power Seminar
Akihabara Convention Center, Tokyo
November 8, 2007
Register Now »