February
22-25, 2010
Doubletree Hotel
San Jose, California
Whatever your design and verification challenges – productivity, predictability, quality, or risk – meet them head-on at DVCon 2010.
Visit Cadence in Booth #505 to learn more about how Cadence® solutions can help you boost team productivity and focus your engineering resources on where they matter most—innovation and differentiated products.
Tutorial 6: OVM Advanced Topics
Tuesday, February 23, 2010
1:30 - 5:00pm (Fir Ballroom)
As users become more adept at building and reusing Open Verification Methodology (OVM)-based verification IP (VIP), it is natural to leverage that experience to related parts of the verification process. The most obvious one is to apply the OVM to multiple languages, including SystemVerilog, e , and SystemC®. Attendees of this techtorial will learn how to apply the OVM in each of these advanced applications: multi-language, VIP, ABV, low power, and acceleration along with code examples and demonstrations that leverage an integrated development environment (IDE) to increase coding efficiency and correctness.
Tutorial 23: Experience with VIP Interoperability Best Practices
Tuesday, February 23, 2010
8:30 - 12:00pm (Fir Ballroom)
Accellera’s VIP Technical Sub-Committee (TSC) released its Best Practices document in August 2009. This was a collective effort by the TSC members to address the real problem of integrating verification IP components built using Verification Methodology Manual (VMM)- or OVM-based classes under a single verification environment. It contains an entire chapter devoted to introducing the high-level concepts of interoperability and component integration. It outlines a process that the verification environment writer can use to determine which cross-referenced best-practice sub-chapter(s) applies to his or her specific integration challenge.
We will introduce the interoperability solution and share our experience of using the recommendations in the Best Practices document on real-life projects – what worked, what came up short, and our insights into making it better. We will also present our thoughts on additional efforts necessary to make the verification components/environments easy to interoperate.
OVM Found the Bugs, Now How Do We Debug Them Faster?
Wednesday, February 24, 2010
12:30 - 1:45pm (Pine/Cedar Ballroom)
The Open Verification Methodology (OVM) has rapidly changed the verification world, enabling users to find bugs much faster than ever before. Whether you use SystemVerilog or e with OVM advanced capabilities such as low power, acceleration, assertion-based verification (ABV), and VIP, the next great challenge is improving your ability to track down and resolve those bugs faster. Topics will focus on how to apply debug capabilities (including waveform/transaction viewing, signal tracing, and source code annotation) to complex problems such as debugging OVM sequences, bus protocols, and multi-language SoC verification. The panelists will also discuss the types of solutions they want to have in the future and will field questions from both the moderator and the luncheon attendees.
Ever-Onward! Minimizing Verification Time and Effort
Thursday, February 25, 2010
3:30 - 5:00pm (Donner/Siskiyou)
According to the “general” consensus, companies are spending 70% of their total time and effort on verification and the trend is upwards. While IP and reuse have helped constrain total design times, they have, if anything, had a detrimental effect on verification. How do we ensure that we minimize the total amount of time, effort, and engineering expense spent in verification, while maximizing the total design quality? Possible ways out include a greater use of formal verification, migration to enterprise system-level (ESL) solutions, additional use of emulation and physical prototyping, intelligent testbenches, etc. While it can be argued that each of these can add to verification productivity, this panel will attempt to decide which emerging technique provides the best value for your money.
Breaking Through the Efficiency Barrier
Wednesday, February 24, 2010
2:00 - 3:00pm (Oak/Fir Ballroom)
In this session, Cadence President and CEO Lip-Bu Tan will share his insights on how today’s electronics companies can break through the efficiency barrier formed by insurmountable complexity and costs. He will explain how embracing higher abstractions of design and verification, reuse, metrics, and up-front tradeoffs can boost productivity and reduce tail-end iterations. Learn how these improvements will result in reduced SoC realization costs and increased predictability, and how they will ultimately prepare the industry to drive the next wave of technology innovation.
| Cadence
Product Demonstrations |
Visit Cadence in Booth #505 to see demonstrations of our latest solutions, including:
- A holistic low-power design methodology implementing multiple low-power techniques
- OVM for multiple languages: e, SystemVerilog, SystemC
- Mixed-signal verification leveraging plan- and metric-driven processes based on e and Verilog AMS
- Verification IP and automating compliance verification
- Acceleration and emulation technology
| Cadence
Paper Presentations and Panel Discussions |
Hear in-depth perspectives from Cadence technology experts on the following topics:
- Paper: Apples Versus Apples: HVL Comparison Finally Arrives
- Paper: Where OOP Falls Short of Verification Needs
- Paper: Tweak-Free Reuse Using OVM
- Panel: Mixed-Signal Verification of Dynamic Adaptive Power Management in Low-Power SoCs
Visit the DVCon site to view all Cadence conference activities »
