Cadence News – March 2011
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Cadence Opens and Extends Verification IP Catalog for Silcon through System Development

New Verification IP Catalog
A One-Stop Shop

Available now, our new portfolio of Cadence Verification IP (VIP) spans silicon, SoC, and system development to help you reduce verification risk and get the highest-quality devices on the market faster than ever before. Our robust solution combines mature, metric-driven Cadence VIP with Denali IP and memory models; support for all major third-party simulators; extended support for more than 30 mainstream and emerging protocols; and, new use models for hardware/software integration.

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What's Hot

New Unified Custom/Analog Flow
New Unified Custom/Analog Flow
Bold enhancements to the Cadence Virtuoso flow deliver a more productive and predictable approach to analog, custom-digital, RF, silicon/package co-design, and mixed-signal design, implementation and verification. New capabilities for in-design DFM and signoff-accurate power management ensure silicon success down to 20nm!

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Visit Cadence at the TSMC Symposium
Visit Us at the TSMC Symposium
Cadence is a co-sponsor of the 17th annual North American TSMC Technology Symposium, showcasing our latest solutions for design for manufacturing at advanced process nodes, verification using transaction-level models, design implementation, and custom/analog design.

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Functional Verification Webinar Series EDA360 Insider: Opinions and Insights Siemens Tapes Out Ahead of Schedule

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