Customer Newsletter - April 2013

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  Cadence
 

Cadence and TSMC Collaborate on Advanced 16nm FinFETs

 

Cadence and TSMC are collaborating in an ongoing, multi-year agreement to develop the design infrastructure for 16nm FinFET technology. The effort targets advanced-node designs for mobile, networking, servers, and FPGA applications.

The resulting infrastructure will support the design of ultra-low power, high-performance chips.


seperator

Relive CDNLive Silicon Valley--Proceedings Available

Relive your experience at CDNLive Silicon Valley 2013. You can now access the conference proceedings online.

Thanks to our customers, the event was a great success, with nearly 100 technical sessions, dozens of partner demonstrations, and several tutorials. With your Cadence.com login information, you can access technical presentations from the convenience of your desktop or mobile device.


Blog: Videos, Presentations Highlight Front-End IC Design Methodologies

Dealing with front-end IC design challenges? The Front-End Design (FED) Technology Summit, held at Cadence® San Jose headquarters in December, yielded some useful answers.

Access session presentations and videos using your Cadence log-in. Topics include: physical aware synthesis, systematic test implementation methodology, and efficient low-power flow with legacy libraries.


 
 
 
 
 
RivieraWaves Cuts Low-Power IP Debug Cycle 30%

See how Cadence SimVision and IES get Bluetooth 4.1 IP to market faster
Read story
 
 
2 New Technical Webinars for Advanced-Node Design

Get tips for 20nm design and addressing layout-dependent effects
Get event details
 
 
Visit Cadence at TSMC Symposium in Boston

Show highlights leading solutions in IP, advanced nodes and more
Get event details
 


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