Customer Newsletter - December 2012

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Faraday Shrinks ECO Implementation Time from 3 Days to 1 Hour

Faraday is a leading provider of application-specific integrated circuit (ASIC) designs. To deliver these designs quickly and consistently to their customers they needed to update their engineering change order (ECO) flow with an automated and proven solution.

Using new capabilities in Cadence Encounter Conformal ECO Designer, Faraday significantly reduced turnaround time, risk and cost in delivering highly customized solutions to its customers.


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seperator

Industry’s First Design IP and Verification IP for Ethernet-based Automotive Connectivity

Cadence recently announced availability of the industry’s first Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers.

Together, both IP help speed today’s newest automotive requirements to market, including improvements to in-vehicle safety, comfort, and infotainment as well as reductions in network complexity and cabling costs.


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Blog: Q&A -- Jiayuan Fang Discusses Sigrity, Signal Integrity, and 3D-ICs

In July 2012 Cadence announced its acquisition of Sigrity, a leading provider of signal integrity (SI) and power integrity (PI) analysis tools for chip, package and board. Jiayuan Fang, Sigrity founder and CEO, joined Cadence as vice-president of R&D for high-speed design in the Silicon-Package-Board (SPB) group.

In this interview Fang discusses Sigrity and its products, the Cadence acquisition, applications of Sigrity technology, and the SI/PI needs of 3D-ICs.


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Layout-Dependent Effects (LDE) Impact 20nm Design Success

Don't let LDE stand between you and your next smart device
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Nufront Develops Mobile Computing Chip in Record Time

Cadence Palladium XP hot-swap technology is key to success
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Join Cadence at DesignCon

Meet Sigrity and Allegro experts, Jan. 28-31, in Santa Clara
Event details

 


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