Customer Newsletter - September 2012

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Industry's First DDR4 Design IP Solutions Are Now Proven in 28nm Silicon

The industry's first DDR4 design IP solutions, the Cadence DDR4 SDRAM PHY and memory controller design intellectual property (IP) family, have been proven in silicon on TSMC's 28HPM and 28HP process technologies.

The Cadence silicon-proven PHY family includes a high-speed implementation of the DDR4 PHY that enables next-generation computing, networking, cloud infrastructure, and home entertainment devices, while offering interoperability with current DDR3 and DDR3L standards.


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seperator

Samsung Speeds SoC Level Validation Using Cadence Tools

In early 2012, Samsung decided to add a PCI Express interface to its SSD controllers to increase the data transfer performance. This addition significantly increased the challenges faced in device and software validation.

Using Cadence Accelerated Verification IP in a Palladium XP-based environment, Samsung is able to dramatically speed validation for early firmware/driver integration and debug.


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Blog: Q&A: Martin Lund Brings User Perspective to Semiconductor IP

Former Broadcom executive Martin Lund joined Cadence earlier this year as Senior Vice President of R&D for the SoC Realization Group.

In this interview Martin Lund talks about his background, the charter of the SoC Realization Group, the challenges of SoC design and IP integration, the emergence of the "IP Factory," and trends in verification IP.


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Newly-Released Cadence Mixed-Signal Methodology Guide

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Last Chance to Register for MemCon!

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