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IP: Crucial to EDA's Evolution

No doubt you’ve seen the market research that supports the promise of the Internet of Things (IoT): 1 billion mobile devices in 2014 (a quarter of which will be tablets); 50 billion other devices in the IoT universe by 2020; 3.3 ZB of data traffic annually, growing 25 percent a year.

Staggering potential. But how are we going to design to and for that kind of growth? One way is by leveraging IP—the subject of this edition of the Cadence® customer newsletter. That kind of growth and the complexity of the systems we’re designing today mean IP and VIP become a crucial foundation to system and subsystem design and engineering productivity. And this is at the heart of the evolution of EDA today.

To understand the evolution, consider Cadence Fellow Chris Rowen’s vision at CDNLive in March. Data—how it’s processed, moved and stored—defines how we architect systems today. And the speed of change and the power, performance, and area demands of IoT require a more holistic approach to system design. Consider, too, Cadence Senior Vice President Nimish Modi's description of how we’re redefining what EDA means to customers—moving from “just tools” to system enablement. For systems designers, this means EDA isn’t just about productivity, it’s about possibility. And central to that is IP.

Brian Fuller
Editor-in-Chief


P.S. Don’t forget to join us at DAC in June! Cadence will be out in force in San Francisco, hosting technical theater presentations, demos, insightful breakfast and lunch panels, and paper sessions, not to mention the hugely popular Denali party. We will see you there!

   Explore What IP Can Do For You
 
Article: How DSP Cores Can Lower Power Consumption for Always-On Subsystems
One of the most efficient tactics to lower power when developing always-on subsystems for voice/facial/visual recognition, gaming, health and fitness, and automotive applications is to use optimized cores instead of general-purpose cores as much as possible.
Read article »

Q&A: How MIPI IP Shortens Development Time for ISP Algorithms
Richard Sproul and Mark Lewis, principal design engineers at Cadence, discuss the challenges in developing image system processing (ISP) algorithms and how MIPI IP can help shorten the development cycle.
Read article »

Article: PCI Express Gen 4—a Big Pipe for Big Data
Learn how the rapid adoption of a new interface specification, PCI Express Gen 4, is key to the continued success of the electronics industry, but also poses a number of challenges that design and verification teams need to consider today.
Read article »

Video: Saving Time and Money with Configurable Processor in Joint CPU and DSP Development Environment
Udi Shaked, Inomize's CEO, explains how Cadence Tensilica® Xtensa® configurable processors supported fast time to market while meeting the cost, power, and performance requirements of their customized ASICs.
Watch video »

Videos: Whiteboard Wednesdays
Check out Whiteboard Wednesdays, a new video blog series that will shed some light and provide some practical insights on how to address a variety of IP-related design challenges.
Watch videos »

Q&A: Interconnect IP Experts
Read this archived online chat and learn about issues relating to performance analysis and functional verification of SoCs containing advanced interconnect IP.
Read Q&A »

New IP Website
Want to learn more about Cadence’s IP offerings? Explore our new IP website for verification, interface, memory, and other IP cores, plus datasheets, partner info, and support resources.
Visit site »

   Cadence on the Road
 
TSMC Technology Symposium 2014—April 22, San Jose, CA; April 29, Boston, MA; May 1, Austin, TX
Join Cadence as we showcase our leading solutions for TSMC technologies in the areas of IP, mixed signal, design for manufacturing, signoff, characterization, advanced nodes, and 3D-IC.

Linley Mobile Conference 2014—April 30-May 1, Santa Clara, CA
This two-day conference features in-depth technical discussions of market trends and technical issues facing designers of mobile devices, including a presentation on “Architectural Requirements for Always-On Subsystems” by Tensilica Founder and Cadence Fellow Chris Rowen.

Club T Israel 2014—May 13, Tel Aviv, Israel
ClubT—the annual Verification Users Event—is a great opportunity to meet and network with verification users and Cadence R&D, to share experiences, ideas, and insights, and to gather information on the best available verification solutions.

CDNLive EMEA 2014—May 19-21, Munich, Germany
Paper presentations, keynotes, demos—these are a few of the exciting activities slated for CDNLive EMEA 2014. Come to the conference to meet with the Cadence tech experts who develop your tools, to share ideas and best practices with your peers, and to hear from industry experts.

DAC 2014—June 1-5, San Francisco, CA
As the Design Automation Conference (DAC) returns to San Francisco in 2014, Cadence is excited to be a Platinum Sponsor and play a prominent role at this premier technical event. You’ll find Cadence at Booth 2616, ready to share a variety of demonstrations, presentations, and technical sessions. And don’t forget to come to the Denali Party!


 

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