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EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



Cadence Synthesis Technology Speeds Time to Production for Renesas Micro Systems

Encounter RTL Compiler Enables Structural Analysis Capability for Large, Complex ASIC Designs, Improving Utilization by 15% and Helping Reduce Die Size

SAN JOSE, Calif.. 26 Nov 2012

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that Renesas Micro Systems Co., Ltd. has adopted the Cadence® Encounter® RTL Compiler for synthesis, highlighting a utilization improvement of 15 percent, area reduction of 8.4 percent, quick turnaround time, and cost reduction for complex ASIC designs.

“Renesas Micro Systems has been working very closely with Cadence to develop best-in-class netlist analysis flows that provide early insights into potential structural issues and inefficiencies. Encounter RTL Compiler solved a problem we had been grappling with for a long while,” said Kazuyuki Irie, chief professional, SoC Development Division of Renesas Micro Systems. “With our prior flow, we were frustrated with all the additional place-and-route cycles we were burning each time we analyzed and resolved problems with hot spots and routability. The Cadence technology offers us a faster and more cost-efficient way to get to production silicon.”

In today’s ASIC design development, there is an increased demand for ultra large-scale, high speed, and complex designs, and Renesas Micro Systems is focused on high-density layout, high speed, and short turnaround time for its ASIC designs. In the past, it was difficult for company engineers to fix serious routability issues after running place and route tools, resulting in longer turnaround times; if engineers identified hot spots, they were forced to run place and route tools to assist with maximum utilization, adjustment of placement congestion, floorplanning and circuit optimization.

Encounter RTL Compiler is unique in that it enables an environment for the structural analysis of a netlist early in the flow. This allows Renesas Micro Systems engineers to identify problematic structures in their designs before conducting place and route. By applying this methodology, they have been reducing turnaround time and easing congestion hot spots, which allows them to further improve utilization and reduce the die size.

In several ASICs—down to 28 nanometers--that have been manufactured, Renesas Micro Systems has reported overall utilization improved by as much as 15 percent over results from the company’s prior methodology. By leveraging Encounter RTL Compiler, Renesas Micro Systems successfully completed several complex ASIC designs in a shorter period of time with reduced die size.

“Like many other technology companies, Renesas Micro Systems is seeking an edge in time-to-market and cost,” said Dr. Chi-Ping Hsu, senior vice president of research and development, Silicon Realization Group, at Cadence. “As a key technology in the Cadence RTL-to-signoff flow, RTL Compiler offers unique capabilities that can get products to market faster while meeting today’s aggressive die size requirements.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com


Cadence, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
 
케이던스 코리아(유)
경기도 성남시 분당구
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