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EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



Cadence Announces Tapeout of 14nm Test-chip with ARM Processor and IBM FinFET Process Technology

14-nanometer SOI FinFET Process Leverages Strong Ecosystem Partnerships Between EDA, Foundry and IP Providers to Deliver Significant Power Savings Potential

SAN JOSE, Calif.. 30 Oct 2012

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today the tapeout of a 14-nanometer test-chip featuring an ARM Cortex®-M0 processor implemented using IBM’s FinFET process technology. The successful tapeout is the result of close collaboration between the three technology leaders as they teamed to build an ecosystem to address the new challenges from design through manufacturing inherent in a 14-nanometer FinFET-based design flow.

The 14-nanometer ecosystem and chip are significant milestones of a multi-year agreement between ARM, Cadence® and IBM to develop systems-on-chip (SoCs) at the advanced process nodes of 14 nanometers and beyond. SoCs designed at 14 nanometers with FinFET technology offer the promise of a significant reduction in power consumption.

"This chip represents a major milestone for advanced node process technology, achieved through tight collaboration among experts at the three companies,” said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “FinFET designs offer significant advantages to the design community, but also require advanced foundry support, IP and EDA technology to meet the considerable challenges. Cadence, IBM and ARM are collaborating to address these challenges and develop an ecosystem that can support 14-nanometer FinFET development for a broad range of production designs.”

The chip was developed to validate the building blocks of foundation IP for 14-nanometer design. In addition to the ARM processor, SRAM memory blocks and other blocks were included that provide the characterization data necessary for foundation IP development for FinFET-based ARM Artisan® physical IP.

“Each move to smaller geometry brings new challenges that require deep collaboration among ecosystem leaders in the SoC design chain,” said Dipesh Patel, vice president and general manager, Physical IP Division at ARM. “With 14-nanometer design, many of these challenges center on FinFETs, and our work with Cadence and IBM has focused on answering the key questions about how to make 14-nanometer FinFET design viable and economically feasible.”

ARM design engineers incorporated an ARM Cortex-M0 processor using 14-nanometer FinFET technology built on IBM’s silicon-on-insulator (SOI) technology, which offers an optimal performance/power profile. A comprehensive 14-nanometer double patterning and FinFET support methodology was employed, with engineers using Cadence technology to design the FinFET 3D transistor chip.

“The tapeout of this 14-nanometer test chip is the culmination of the significant progress we have made with FinFET on SOI utilizing it's built in dielectric isolation,” said Gary Patton, vice president of IBM Semiconductor Research and Development Center. “In fact, Cadence and ARM have collaborated on a design solution to tape out this test chip based on IBM’s FinFET technology. We continue to collaborate to deliver on the promise of superior power, performance, and variability control of fully depleted SOI FinFET devices at 14 nanometers and beyond.”

To succeed, engineers required support for 14-nanometer and FinFET rule decks, as well as enhanced timing analysis. The chip was implemented using the Cadence® Encounter® Digital Implementation (EDI) System with ARM 8-track 14-nanometer FinFET standard cell libraries designed with Cadence Virtuoso® tools. EDI System provides advanced digital capability required for implementing designs based on 14-nanometer FinFET-based DRC rules, and incorporates new GigaOpt optimization technology to realize power and performance benefits offered by FinFET technology. In addition, the solution also uses production-proven double patterning-correct implementation capabilities. Encounter Power System, Encounter Timing System and Cadence QRC Extraction provide 14nm timing and power signoff capabilities supporting 14-nanometer FinFET structures.

About Cadence Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com


Cadence, Encounter, Virtuoso and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
 
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