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EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



Cadence Announces DFI 3.0-compliant Design and Verification IP

Enables Rapid Deployment of Next-Generation SoCs Supporting DDR4 Memory

SAN JOSE, Calif.. 19 Sep 2011

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced it is offering a comprehensive suite of solutions in support of the latest DDR PHY Interface (DFI) 3.0 specification (also announced today by the DFI Technical Group). Enabling the development of chips and systems to support the emerging DDR4 memory standard, the specification defines an interface protocol between DDR memory controllers and PHYs. Cadence supports the specification across its DDR DRAM Controller IP, DDR PHY IP, and as part of the Cadence Verification IP Catalog. Cadence introduced the industry’s first DDR4 IP memory solution in April of this year.

“Our customers require DFI-compliant design and verification IP that will enable them to be first to market with next-generation SoCs that support the emerging DDR4 standard,” said Marc Greenberg, director of marketing, SoC Realization, Cadence. “Our close working relationship with the DFI Technical Group ensures that we offer integration-ready DFI solutions when the specification becomes available.”

DFI interface adoption continues to rise as designers seek ways to reduce the time-to-market and cost of their SoCs. Cadence has over 400 design wins for DDR controllers and PHYs, and all DDR3 designs currently in development use the DFI interface. This makes DFI 3.0 support critical to customers who must deliver solutions in support of the emerging DDR4 standard.

About DFI 3.0
DFI 3.0 defines methods for interfacing to DDR4 devices with proposed data rates up to 3.2 Gbits/second per pin – more than 50 percent faster than the current DDR3 standard – and extends the low-power interface that was introduced with DFI 2.1. By accounting for frequency and power challenges at high speeds, the new standard helps ensure exceptional performance in systems using DDR4 memory. The preliminary specification is available now for download at www.ddr-phy.org.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Joany Draeger
Cadence Design Systems
(408) 428-5220


Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
 
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