Home > Cadence Korea > Cadence Korea


EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



Cadence Unveils New Virtuoso Advanced Node for 20nm Design

Leading Companies Benefiting from New Breakthrough Cadence Methodology Spanning Specification to Signoff for Advanced-Node Designs

DESIGNCON, SANTA CLARA, Calif.. 28 Jan 2013

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced the availability of Virtuoso® Advanced Node, a new set of breakthrough custom/analog capabilities designed specifically for the advanced technology nodes of 20 nanometers and below. Built on the industry-leading Cadence® Virtuoso custom/analog technology, Virtuoso Advanced Node features unique and innovative capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter® RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of complex mixed-signal chips that power today’s leading consumer electronics devices.

The new Virtuoso Advanced Node environment uses a novel color-aware layout approach to tackle 20- and 14-nanometer designs.


The new and advanced Virtuoso technologies address the toughest challenges facing engineers, including layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. They integrate seamlessly with the Cadence Integrated Physical Verification System (IPVS) — a foundry-qualified technology for signoff DRC and DPT checking — to conduct on-the-fly checks that reduce layout iterations.

“As a semiconductor leader, we have moved aggressively to meet the new complexities of 20-nanometer technology to stay on the cutting edge of design,” said Pierre Dautriche, senior director at STMicroelectronics. “The new Virtuoso advanced-node capabilities have contributed to our transition by providing high-quality automation for our custom/analog chips. Virtuoso Advanced Node takes into account the idiosyncrasies of designing at 20 nanometers and ensures a much more efficient development cycle.”

Features and Capabilities:
LDE analysis using incremental layout — Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end. It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle. LDEs — such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics -- are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.

When this technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time. By methodically building and checking the design, the designer should eliminate massive “rip ups” and “reroutes” that can be found at the end if the circuit wasn’t checked along the way.

Double patterning and color-aware layout — Double patterning, a manufacturing requirement at 20 nanometers, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “coloring” challenges to designers. Virtuoso Advanced Node delivers real-time automated color-aware, design-rule-driven layout to enable the creation of area-optimized layout. It provides engineers the ability to match, lock and store colors on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix.

New routing layers — Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors. Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.

Developed specifically for the most cutting-edge designs, the Virtuoso Advanced Node options do not replace the industry-leading 6.x version of the Virtuoso technology, which targets mature and mainstream geometries, and which will continue to be enhanced by Cadence.

“Moving to smaller geometries always creates new obstacles, but the move to 20 nanometers has been especially challenging for our customers, many of whom are reporting that layout is taking two to five times as long as for 28 nanometers on the same circuit,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “Virtuoso Advanced Node enables design teams to optimize their designs for performance, power and area while reducing or even eliminating tasks that would make 20-nanometer design much more time consuming and labor intensive.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com


Cadence, Encounter, Virtuoso and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
 
케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
전화번호: 031-728-3111(代)
Regional Offices »