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EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



Imec Teams With Cadence to Present Automated Design-for-Test (DFT) Solution for 3D Memory-on-Logic

LEUVEN, Belgium. 22 Jan 2013

At the European 3D TSV Summit in Grenoble, France on January 22-23, 2013, imec, a world-leading nano-electronics research institute, today announced that together with Cadence Design Systems they have developed, implemented and validated an automated 3D Design-for-Test (DFT) solution to test logic-memory interconnects in DRAM-on-logic stacks. The solution, based on Cadence® Encounter® Test technology, was verified on an industrial test chip containing a logic die and a JEDEC-compliant Wide-I/O Mobile DRAM.

Memory-on-logic 3D stacks offer the possibility of heterogeneous integration with dense low-power inter-die interconnects. Hence, they are amongst the first 3D products that will come on the market, enabling next-generation high-performance low-power mobile applications. Recently, JEDEC has released a standard (JESD-229) for stackable Wide-I/O mobile dynamic random access memories (DRAMs) specifying the logic-memory interface. Unlike many previous DRAMs, the standard contains boundary scan features to facilitate interconnect testing. Imec and Cadence now present a design-for-test (DFT) architecture and corresponding automatic test pattern generation (ATPG) approach. It is an extension of their previously announced logic-on-logic 3D DFT architecture and it supports post-bond testing of the interconnects between the logic die and the DRAM stacked on top of it.

The solution implemented by Cadence and imec includes the generation of DRAM test control signals in the logic die and the inclusion of the DRAM boundary scan registers in the serial and parallel test access mechanisms (TAMs) of the 3D test architecture. The automated design for test solution has been validated on an industrial test chip. The design of the test chip is an interposer-based 3D stacked IC which includes a silicon interposer base die, a 94mm2 logic system-on-chip in 40nm technology, and a single Wide-I/O DRAM rank. The validation results show that the silicon area of the additional DFT wrapper is negligible compared to the total logic die size (<0.03%). Moreover, the test pattern generation was very efficient (tens of patterns, generated in only a few seconds) and effective (100% coverage of the targeted faults). All 3D-DFT logic in the logic die was automatically inserted with Cadence Encounter RTL Compiler while the Interconnect test patterns were generated with Encounter Test ATPG.

“This 3D memory-on-logic DFT solution is another big step forward toward market introduction of 3D-stacked IC for next-generation high–performance, low-power mobile applications,” said Bassilios Petrakis, product marketing director for the Encounter Test product family at Cadence. “Our collaboration with imec has enabled the creation of an industry-leading solution that enhances efficiencies of 3D-IC design for our customers.”

“Teaming up with Cadence enables us to automate the insertion of our DFT circuitry in a given design, and to automate the interconnect test pattern generation. Such automated flows make our technology valuable for the industry. We are confident that we can also handle the DFT features that start to emerge in other 3D memory standards,” said Erik Jan Marinissen, Principal Scientist at imec.

Part of the work has been performed in the project ESiP, which is co-funded by the ENIAC Joint Undertaking.

About imec
Imec performs world-leading research in nano-electronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China, India and Japan. Its staff of close to 2,000 people includes more than 600 industrial residents and guest researchers. In 2011, imec's revenue (P&L) was about 300 million euro. Further information on imec can be found at www.imec.be.
Imec:
Hanne Degans
External Communications Officer
Phone: +32 16 28 17 69
Mobile: +32 486 065 175
Hanne.Degans@imec.be


Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a "stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shangai) Co. Ltd.) and imec India (Imec India Private Limited).
 
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