The Global Route Environment (GRE) provides the technology and methodology to capture as well as adhere to a designer’s intent. In the Allegro® GRE Interconnect Flow Planning course, you apply this technology and methodology to convert your design intent into the final board design.
You develop the first stage of flow planning by creating bundles manually, applying constraints to them, and editing the bundles. After this initial stage, you develop and define the flow of the bundles. After defining the flow, you plan (or route) it. You explore the three phases of planning, spatial, topological, and accurate, in detail.
After completing this course, you will be able to:
o Understand GRE terminology and technology
o Create, edit, and use bundles
o Create and modify the flow of a bundle
o Understand the entire planning process
o Identify the three stages of planning, spatial, topological, and accurate
o Have multiple designers work on the same design at the same time.
Software Used in This Course
o Allegro PCB Designer product license with the GRE-Full Router product option.
o SPB 16.5
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
o Introduction to the Interconnect Flow Designer (IFD) and GRE
o Creating and Using Bundles
o Editing Bundles
o Flow Editing
o Planning Overview
o Spatial Planning
o Topological and Accurate Planning
o Increasing Throughput
o PCB Designers
You must have experience with or knowledge of the following software:
o Allegro PCB Editor