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Virtuoso Connectivity-Driven Layout vIC 6.1.5

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Availability
DatesLocations
10 Nov 2014 - 11 Nov 2014Bundang, Pangyo , Korea정원초과

Course TitleVirtuoso Connectivity-Driven Layout vIC 6.1.5
Course CategoryCustom IC Design – Virtuoso
Duration2 days
Product VersionvIC 6.1.5
InstructorSE CHOI

Course Description

The Virtuoso Connectivity-Driven Layout course focuses on the added functionality and enhanced productivity made possible by the Virtuoso Layout Suites XL and GXL advanced automation. You will gain the knowledge and skills needed to implement this capability within your design environment through lecture, discussion, demonstrations, and related labs. New features covered in this course are:

o   Constraint Enhancements including:

o   Process Rules Editor, Constraint Manager, right-mouse-button context sensitive constraint menu.

o   Enhanced Annotation Browser functionality

o   Added routing capability using the Navigator

o   Interactive routing enhancements including:

o   Wire Editor, point-to-point, guided routing, bus routing, finish net and finish bus

o   Synchronous Copying

o   Synchronous Cloning

o   Dynamic Abstract Generation

o   Module Generator(ModGen) Enhancements including:

o   Greater capacity, enhanced guardring creation and editing, enhanced routing capability and dummy cell control

o   Connectivity Extraction from the Substrate/Well

o   Guardring Enhancements

This course is the next step after the Virtuoso® Layout Design Basics course. In this layout course, you leverage the automation that connectivity-driven layout offers to help you attain first time silicon success. You will understand and exercise the capabilities in the Virtuoso® Layout Suites XL and GXL tiers to improve your layout productivity.

You locate relevant information using the Cadence® Help system, manage the workspace design environment, utilize the connectivity binder/extractor to validate consistency between schematic and layout, implement synchronous clones to streamline layout, and apply additional constraints using the Process Rules Editor to override existing design rules.

You place devices and pins and create interconnect by using the wire editor, point-to-point editor, and the guided routing editor. Using the Virtuoso Space-based Router, you auto-route a device-level design completely within the Virtuoso environment.

You analyze and update designs with an Engineering Change Order (ECO) process. By applying the Configure Physical Hierarchy(CPH) tool, you examine and implement design changes. You also use the Module Generator to examine and create a layout module.

An appendix detailing the enhancements in the latest IC 6.1.5 release is also included.

Learning Objectives

After completing this course, you will be able to:

o   Implement the new and improved features and methodologies in the IC6.1.5 release.

o   Implement the new workspace environments

o   Apply improved constraints and connectivity

o   Implement the Process Rules Editor

o   Use pin swapping and abutment

o   Implement new interactive and automatic routing

o   Analyze and update a design with improved ECO techniques

o   Implement the Configure Physical Hierarchy tool

o   Apply the new Module Generator software

o   Review the enhancements for this release (including the L, XL and GXL tiers)

Software Used in This Course

o   Virtuoso Layout Suite XL

o   Virtuoso Layout Suite GXL

Software Release(s)

o   IC615

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

 

o   The Design Environment

o   Design Creation and Placement

o   Connectivity

o   Constraints

o   Interactive Routing


            o   Auto Routing within Virtuoso (VSR)

o   Module Generator Enhancements (ModGens)

o   Review of the detailed list of IC6.1.5 enhancements to L, XL and GXL

o   Course Review and Q & A

Audience

o   Layout Engineers

o   CAD Managers

o   CAD Developers

Prerequisites

You must have experience with and knowledge of the following:

o   Layout techniques

o   Logic symbols

o   Schematic symbols

o   MOS devices

o   Unix/Linux

Or you must have completed the following courses:

o   Virtuoso Layout Design Basics vIC6.1.5

o   Virtuoso Layout Suite Update -v6.1.4

Related Courses

 Virtuoso Chip Assembly Router-v11.2.41
 Virtuoso Schematic Editor vIC.6.1.6
 Virtuoso Design Environment Setup vIC.6.1.4
 
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