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Encounter Digital Implementation (Flat)_11.1

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Course TitleEncounter Digital Implementation (Flat)_11.1
Course CategoryDigital IC Design – Encounter
Duration3 Days
Product VersionEDI 13.1

Course Description

In this course, you explore high-level design planning and implementation by using the Encounter® Digital Implementation software. You learn several techniques for floorplanning and placement while implementing timing closure strategies. You run the detail router to route a design, fix routing violations, and use timing and signal integrity options.

 

Other topics in this course include extracting parasitics, creating clock trees, running delay calculation, and using database access commands. You also explore wire editing, metal fill, ECO, and physical verification.

                                                          

This course was formerly called Floorplanning, Physical Synthesis, Place and Route (Flat).

Learning Objectives

After completing this course, you will be able to:

 

o   Floorplan a design

o   Place blocks and standard cells

o   Run scan optimization

o   Run Trial Route and route the power

o   Estimate parasitics and generate timing information

o   Analyze routing congestion

o   Create clock trees

o   Run power analysis

o   Modify net attributes

o   Edit wires manually

o   Route with signal integrity options

o   Extract RC data

o   Optimize and close timing

o   Fix routing violations

o   Route in ECO mode

o   Run database access commands

o   Run foundation flow scripts

Software Used in This Course

o   Encounter Digital Implementation System XL

Software Release

o   EDI131

Course Agenda

Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.

 

 

o   Floorplanning the design

o   Planning power

o   Routing power

o   Placing cells and blocks

o   Optimizing and reordering scan chains

o   Analyzing route feasibility using Trial Route

o   Extracting parasitics and analyzing timing

o   Running optimization and closing timing

o   Implementing the clock tree

o   Analyzing power

o   Selecting routing attributes and options

o   Performing wire editing and metal fill

o   Running signal integrity

o   Running database access commands

o   Implementing an engineering change order

o   Writing out a design

o   Creating and running Foundation Flow scripts

Special Note

This course does not include RTL synthesis. For detailed knowledge of running RTL synthesis, take the Encounter® RTL Compiler course.

Audience

o   CAD Engineers

o   Chip Designers

o   Physical Layout Designers

Prerequisites

You must have experience with or knowledge of:

o   Design methodology

o   Place and Route

 
케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
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