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Incisive SystemC, VHDL, and Verilog Simulation v11.1

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Course TitleIncisive SystemC, VHDL, and Verilog Simulation v11.1
Course CategoryFunctional Verification – Incisive
Duration3 Days
Product Versionv11.1

Course Description

This course addresses Incisive® mixed-language (SystemC®, VHDL, and Verilog®) event-driven digital simulation. The course takes you through the compilation, elaboration, simulation, and interactive debug process, at each step explaining the most commonly used options. This course treats the SystemC, VHDL, and Verilog languages equivalently. You can do the labs in your choice of language.

Learning Objectives

After completing this course you will be able to:

o   Compile, elaborate, link, and simulate a design: Understand how to specify the inputs and outputs at each phase, configure the design, and control each process for effectiveness and optimal performance.

o   Debug a design with the textual interactive simulation interface: Briefly examine most of the interactive commands for the purpose of understanding what capabilities are available and how you can use them in a script to drive batched regression tests; practice these capabilities in the context of a scripted debug scenario.

o   Debug a design with the graphical interactive simulation interface: Examine many of the capabilities of the feature-rich SimVision graphical simulation analysis environment; practice these capabilities in the context of a scripted debug scenario.

o   Utilize some of the other tools available to assist your simulation-related efforts to: Verify your platform's patch level, protect your intellectual property, “lint” your design and filter and sort the analysis report, manage your library of compiled design objects, compare simulation traces, package your design for transmittal, and much more.

o   Optionally: Understand the issues involved with mixed-language instantiation, simulation, and debugging; Examine the mechanics of interconnecting components of multiple languages; Choose and simulate a mixed-language design configuration containing at least one HDL component and at least one SystemC component.

Software Used in This Course

o   Incisive Enterprise Simulator - XL

Software Release(s)

o   INCISIV111

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.


o   Incisive simulation introduction

o   Setting up the simulation environment

o   Compiling your design

o   Optionally: Linking SystemC components

o   Elaborating your design

o   Simulating your design

o   Using the irun utility

o   Debugging with the textual interface

o   Debugging with the textual interface (continued)

o   Debugging with the graphical interface

o   Employing simulator-related utilities

o   Optionally: Simulating mixed-language designs


o   Hardware or software design or verification personnel who are already familiar with SystemC, VHDL or Verilog, and basic design verification techniques, and who intend to use Incisive simulation.


You must have:

o   Familiarity with the SystemC, VHDL or Verilog languages.

o   Familiarity with hardware and software design and verification methodology.

o   Basic UNIX literacy; you must know how to navigate the file system and open, edit, move, and delete files.

케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
전화번호: 031-728-3111(代)
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