Home > Cadence Korea > Cadence Korea

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *



EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



TSMC and Cadence Deliver 3D-IC Reference Flow for True 3D Stacking

SAN JOSE, Calif.. 19 Sep 2013

Highlights:
  • New reference flow enhances CoWoS™ (chip-on-wafer-on-substrate) chip design
  • Flow certified using a memory-on-logic design with a 3D stack
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that TSMC has collaborated with Cadence to develop a 3D-IC reference flow which features innovative true 3D stacking. The flow, validated on a memory-on-logic design with a 3D stack based on a Wide I/O interface, enables multiple die integration. It incorporates TSMC 3D stacking technology and Cadence® solutions for 3D-IC, including integrated planning tools, a flexible implementation platform, and signoff and electrical/thermal analysis.

3D-IC technology enables companies to seek power/performance advances by opening up a new opportunity in addition to moving to advanced geometries. Offering several key benefits for engineers developing today’s complex designs, 3D-ICs deliver higher performance, reduced power consumption, and smaller form factor. Today’s announcement follows work the two 3D- IC leaders announced a year ago with the delivery of TSMC’s CoWoS™ Reference Flow.

“We have worked closely with Cadence to enable true 3D chip development,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With this new reference flow, our mutual customers can move forward confidently with 3D-IC development, knowing that their Cadence tool flow has been validated in silicon with 3D-IC test vehicles.”

“3D-IC represents a dramatic new approach to product integration. It provides a new dimension to Moore’s Law and requires a deep collaboration for a seamless enablement offering,” said Dr. Chi-Ping Hsu, chief strategy officer and senior vice president of the digital and signoff group at Cadence. “This latest reference flow demonstrates real progress in our work with TSMC to make 3D chips not just viable, but an attractive option for addressing chip complexity.”

Tools in the Cadence 3D-IC flow span digital, custom/analog and signoff technologies. They include Encounter® Digital Implementation System, Tempus™ Timing Signoff Solution, Virtuoso® Layout Editor, Physical Verification System, QRC Extraction, Encounter Power System, Encounter Test, Allegro® SiP, and Sigrity™ XcitePI/PowerDC.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
Cadence Newsroom
408-944-7226
newsroom@cadence.com


© 2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Allegro, Encounter, Sigrity, Tempus, Virtuoso and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
 
케이던스 코리아(유)
경기도 성남시 분당구
금곡동 196. 한전기공빌딩 6층
전화번호 : 031-728-3114(代)
Regional Offices »