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EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



UMC Adopts Cadence Physical and Electrical Design-for-Manufacturing Signoff for 28-Nanometer Node

Cadence Accelerates Litho, CMP and LDE Analysis Design-for-Manufacturing Flows for UMC Customers

SAN JOSE, Calif.. 16 Jul 2013

HIGHLIGHTS
  • New flows incorporate the industry’s leading DFM prevention, analysis, and signoff capabilities
  • Cadence technologies selected after extensive benchmark testing
  • DFM solutions to boost productivity and enhance yield for customers
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that after extensive benchmark testing, semiconductor foundry United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (UMC) has adopted the Cadence® “in-design” and signoff design-for-manufacturing (DFM) flows to perform physical signoff and electrical variability optimization for 28nm designs. The flows address both random and systematic yield issues, providing customers with another proven foundry flow for 28nm designs. Developed in collaboration with UMC, these new flows incorporate the industry’s leading DFM prevention, analysis, and signoff capabilities, including Cadence Litho Physical Analyzer (LPA), Cadence Pattern Analysis, Cadence Litho Electrical Analyzer (LEA), and Cadence Chemical-Mechanical Polishing Predictor (CCP) technologies.

At 28nm and beyond, it is critical to accurately predict and automatically fix DFM “hotspots” to accelerate time-to-yield. UMC joins a growing list of leading foundries standardizing on Cadence DFM solutions to boost productivity and yield for customers. The DFM signoff technologies tightly integrate into the Encounter® digital and Cadence Virtuoso® custom/analog implementation and sign-off solutions. This solution delivers a “correct-by-design” capability for customers that models and analyzes the physical and parametric impact of lithography, CMP, and layout dependent effects, and then optimizes the implementation to mitigate the physical and electrical variation on the designs, allowing users to reach their time-to-volume goals.

“To meet our time-to-market goals, DFM solutions at 28nm need to deliver low cost of ownership, accurate silicon predictability and high performance,” said S.C. Chien, vice president of IP & Design Support division at UMC. “After rigorous evaluation, the Cadence DFM technology was selected for its exceptional characteristics in both physical and electrical DFM analysis. Now, we can offer our customers much greater predictability and faster turnaround time for their advanced node designs.”

“At advanced nodes, prevention of potential DFM hotspots and yield limiters before tapeout is imperative to achieving first-silicon success and the highest silicon yields,” said Anirudh Devgan, corporate vice president, Silicon Signoff and Verification, Silicon Realization Group at Cadence. “Working in tight partnership with UMC, we continue to invest in technologies that strengthen our leadership in sign-off technologies, like providing DFM-aware implementation flows for current and future nodes.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
newsroom@cadence.com


© 2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Encounter, Virtuoso and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
 
케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
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