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EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



Cadence Physical Verification System Qualified for TSMC 28nm, 20nm Process

SAN FRANCISCO, Calif.. 04 Jun 2012

DAC Booth #1930 —Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that TSMC has qualified the Cadence® Physical Verification System (PVS) for 28-nanometer design signoff, and completed Phase I certification for TSMC’s 20-nanometer process.

Designers can request a PVS 20-nanometer technology file directly from TSMC for early design exploration, and access TSMC-Online to download 28-nanometer technology files for signoff.

Cadence PVS supports 20-nanometer technology where innovative patterning technology is used. The dedicated PVS engine improves color loop detection accuracy, reduces false errors and provides intuitive error reporting. The Cadence technology also ensures mask decomposition feasibility.

Cadence PVS is integrated with Cadence Virtuoso® custom and Encounter® digital implementation platforms to help designers find and fix errors early in the implementation stage. Integration with Virtuoso includes real-time, in-design design rule checking (DRC) verification; real-time 20-nanometer DPT color loop detection; and incremental DRC correction and verification.

“Our work with TSMC helps ensure that design teams will have advanced implementation and signoff technologies available for SoC design and manufacturing,” said Chi-Ping Hsu, senior vice president of research & development, Silicon Realization Group. “TSMC’s qualification of Cadence PVS at 28 nanometers and early certification for 20 nanometers represents an important joint commitment to deliver convergent verification capabilities for today’s complex mixed-signal SoCs.”

“PVS has successfully completed TSMC’s qualification process for 28-nanometer design signoff,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We worked closely with Cadence to achieve these results, including technical collaboration on 20-nanometer advanced technology.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com


Cadence, Virtuoso, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
 
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