Cadence.com will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST).
Cadence.com login, registration, community posting and commenting functionalities will be disabled.
Home > Cadence Korea > Cadence Korea

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *



EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



Cadence Digital and Custom/Analog Tools Achieve TSMC V1.0 DRM Certification for 16nm FinFET Process

Full certification enables customers to tape out 16nm FinFET designs using Cadence tools

SAN JOSE, Calif.. 15 Apr 2014

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced its digital, custom and signoff tools have received V1.0 Design Rule Manual (DRM) and SPICE certification for TSMC’s 16nm FinFET process, enabling joint customers to begin taping out FinFET-based designs using Cadence® tools. Cadence’s digital, custom/analog and signoff tools have been co-optimized with TSMC’s 16nm FinFET process to enable higher performance, lower power consumption and smaller area for advanced designs.

The Cadence digital RTL-to-signoff and custom/analog tools receiving the V1.0 DRM certification are: Cadence Encounter® Digital Implementation System, Physical Verification System, QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Virtuoso® Schematic Editor, Virtuoso Layout Suite, Virtuoso Analog Design Environment and Spectre® Simulator.

“To drive the continued adoption of advanced process technologies such as 16nm FinFET, customers must be confident that the design tools and manufacturing process have been tested to ensure they work together seamlessly,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We worked closely with Cadence to certify these design tools and incorporate them into the TSMC Reference Flows so our customers can meet their time-to-market goals and stay competitive in advanced technology design.”

“The combination of our early investment in FinFET technology development and long-term partnership with TSMC enabled Cadence to quickly achieve V1.0 DRM certification,” said Dr. Chi-Ping Hsu, senior vice president and chief strategy officer at Cadence. “Several of our customers are already using these tools and flows to design in TSMC’s new process technology to deliver innovative new devices.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
Cadence Newsroom
408-944-7039
newsroom@cadence.com


© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Encounter, Virtuoso, and Spectre are registered trademarks and Tempus and Voltus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
 
케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
전화번호: 031-728-3111(代)
Regional Offices »