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SiP Layout v16.5

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Course TitleSiP Layout v16.5
Course CategorySystem Interconnect Design – Allegro & OrCAD
Duration4 Days
Product VersionSPB16.5

Course Description

In this course, you learn the complete flow of a System in Package (SiP) design, from defining the module outline to placing components, defining a netlist, placement, routing, documentation, and manufacturing output. You also learn the complete design flow for a flip-chip and wire-bonded stacked die module using the Cadence® SiP Layout software.

Learning Objectives

After completing this course, you will be able to:

o   Develop a process flow to suit your design needs

o   Create a cross section and design constraints in your SiP layout database

o   Wire bond a stacked die design

o   Use the 3-D viewer to check your design in three dimensions

o   Route an SiP design using interactive and automatic methods

o   Generate a variety of manufacturing outputs for your SiP design

Software Used in This Course

o   Cadence SiP Layout - XL

Software Release

o   SPB 16.5

Course Agenda

Note that this course can be tailored to better meet your needs contact the Cadence training staff for specifics.


o   User interface

o   Creating I/O components

o   Creating standard die

o   Design constraints

o   Die stack editing

o   3-D viewing

o   Adding discrete components

o   Power and ground rings

o   Wire bonding

o   Routing

o   Conductor planes

o   Degassing

o   Finalizing a design

o   Generating reports

o   Generating manufacturing data


o   IC package and SiP Designers


There are no prerequisites.

케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
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