The Virtuoso® AMS Designer course teaches you how to use the mixed-signal, mixed-language Virtuoso AMS Simulator. It also provides a brief introduction to the Verilog®-AMS mixed-signal modeling language. Lab exercises explore three different simulation use models: the Virtuoso Analog Design Environment, the Virtuoso AMS Designer graphical environment, and command-line control, including verification flow.
Upon completion of the Virtuoso AMS Designer course, you will be able to:
o Run Virtuoso AMS Designer through typical simulations using command-line control, the Virtuoso AMS Environment, and the Virtuoso Analog Design Environment.
o Switch between two analog solvers, Virtuoso Spectre® Circuit Simulator and Virtuoso UltraSim® Full-chip Simulator, to optimize simulation speed and accuracy.
o Create configurations to allow easy replacement of behavioral models with more detailed schematic designs.
o Create simple models with the Verilog-AMS modeling language.
o Apply signal disciplines and control interconnect module placement.
This course is designed for developers who create designs for analog or digital ICs such as:
o IC Designers
o Analog/Mixed-Signal IC Designers
o Digital IC Designers
o ASIC Designers
o Design Engineers
o Chip Designers
o Layout Designers
o Analog Modeling with Verilog-A
o Virtuoso Analog Design Environment
o You should be familiar with the Verilog, Verilog-A, VHDL, or C languages.
o Getting Started
o Introduction to Virtuoso AMS Designer in ADE
o Using the Hierarchy Editor to Control the Configuration
o Using the Virtuoso AMS Environment to Run Simulations
o Command-line Control of Virtuoso AMS Designer
o Introduction to the Verilog-AMS Language
o Verilog-AMS Module Content
o Discipline Resolution
o Using the UltraSim Solver in AMS
o Using the AMSD Incisive® Flow for Design Verification
o Migrating Designs to AMS
o Introduction to the VHDL-AMS Language (optional)
o VHDL-AMS Processes (optional)
o VHDL-AMS Implementation (optional)