Home > Cadence Korea > Course Detail

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

 


RTL Compiler & Physical synthesis_11.1

Back to course catalogue
Availability
No dates are currently scheduled. To express interest in this course, contact Cadence Training

Course TitleRTL Compiler & Physical synthesis_11.1
Course CategoryDigital IC Design – Encounter
Duration3 Days
Product Version11.1

Course Description

In this course, you explore the features of the Cadence® Encounter® RTL Compiler with global synthesis technology.

You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, optimize for low power, and interface with other tools.

Learning Objectives

After completing this course, you will be able to:

  • Apply the recommended global synthesis flow using Encounter RTL Compiler.
  • Navigate the design database and manipulate design objects.
  • Constrain designs for global synthesis and run static timing analysis.
  • Optimize RTL designs for timing and area using several strategies.
  • Diagnose and analyze synthesis results.
  • Use the extended datapath features of the compiler.
  • Analyze and synthesize the design for low-power.
  • Interface with other tools and place-and-route flows.

Software Used in This Course

  • Encounter RTL Compiler with physical

Software Release(s)

  • RC111

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.

Day 1

  • About this Course
  • Introduction to Encounter RTL Compiler
  • HDL Modeling
  • Synthesis Flow
  • Datapath Synthesis
  • Optimization Strategies

Day 2

  • Low-Power Synthesis
  • Interface to Other Tools
  • Test Synthesis

Day 3

  • Physical Synthesis
  • Advanced Synthesis Features
  • RAK(Rapid Adoption Kits)

 

Audience

  • ASIC Designers
  • Digital IC Designers
  • Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

  • Any HDL such as Verilog® (recommended) or VHDL

Or you must have completed the following courses:

·         Verilog Language and Application v9.2

Related Courses

·         Logic Equivalence Checking with Encounter Conformal EC

·         Floorplanning, Physical Synthesis, Place and Route (Flat)

 
케이던스 코리아(유)
경기도 성남시 분당구 판교로
344 엠텍IT타워 9층
(구. 삼평동 688-1)
전화번호: 031-728-3114(代)
Regional Offices »