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EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



Cadence News

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December
20 Dec 2010: Cadence Virtuoso Accelerated Parallel Simulator Wins Elektra Electronics Industry Awards 201015 Dec 2010: Electronic Design Magazine Awards Cadence Encounter Best Electronic Design Product for 201008 Dec 2010: SMIC Adopts Cadence DFM and Low-power Silicon Realization Technology for 65-Nanometer Reference Flow07 Dec 2010: Cadence C-to-Silicon Compiler Supported in Fujitsu Semiconductor’s ASIC Flow for System Realization06 Dec 2010: Media Alert: Cadence to Present and Showcase Technology at RTI's 3D Architectures for Semiconductor Integration and Packaging Conference
November
16 Nov 2010: Cadence Senior Vice President and Chief Financial Officer Geoff Ribar to Present at the Nasdaq OMX 25th Investor Program15 Nov 2010: Open-Silicon Achieves Ultra High Performance Using Cadence Silicon Realization Technology to Tape-Out Breakthrough 2.4 GHz ASIC Processor05 Nov 2010: MEDIA ALERT: Cadence Demonstrates EDA360 Vision and Ecosystem Support at ARM Technical Conference 2010
October
27 Oct 2010: Cadence Reports Q3 2010 Financial Results26 Oct 2010: Cadence Unveils Holistic Approach to Silicon Realization18 Oct 2010: Cadence and Xilinx Introduce FPGA IP Ecosystem Microsite08 Oct 2010: Cadence Announces Third Quarter 2010 Financial Results Webcast
September
27 Sep 2010: Cadence Offers Optimized Implementation Methodology for Silicon Realization of New ARM Cortex-A15 MPCore Processor27 Sep 2010: Cadence Announces Chief Financial Officer Transition Plan27 Sep 2010: Sunplus Reduces Design Cycle on High-Speed Multi-Million-Gate SoC Using Cadence Encounter Digital Implementation System16 Sep 2010: SMIC Adopts Cadence Silicon Realization End-to-End Product Line for 65-40nm Design13 Sep 2010: Global Unichip Boosts Design Productivity with Cadence Encounter Timing System08 Sep 2010: Global Unichip Expands Portfolio of Cadence Technology to Speed IP Development
August
30 Aug 2010: Andes Technology Adopts Cadence Digital Front-End Low-Power Flow18 Aug 2010: Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Deutsche Bank Technology Conference04 Aug 2010: Cadence Aligns Workforce to Deliver on EDA360 Vision
July
29 Jul 2010: Realtek Semiconductor Selects Cadence Design Systems as its Strategic EDA Solutions Provider28 Jul 2010: Cadence Reports Q2 2010 Financial Results - Updated For Form 8-K Filed August 4, 201022 Jul 2010: Fujitsu Adopts Cadence Encounter Conformal ECO Designer21 Jul 2010: Cadence and ARM Collaborate to Create an ARM-Optimized System Realization Solution20 Jul 2010: Fujitsu Adopts Cadence Chip Planning Technology20 Jul 2010: Cadence Develops Die Model Enabling Comprehensive Chip-Package Co-Design Solution with Fujitsu19 Jul 2010: NationZ Selects Cadence as Provider of Choice on Leading-Edge SoC Designs at Advanced Node19 Jul 2010: Hitachi Achieves 10,000 Times Performance Boost Using Cadence Technology to Verify Complex Design19 Jul 2010: Hitachi Raises System-Level Simulation Performance 100x with Cadence Palladium Transaction-Based Acceleration15 Jul 2010: Cadence QRC Extraction adopted by STMicroelectronics for 40nm Analog/Mixed-Signal Design15 Jul 2010: Casio Cuts Design Cycle Time and Improves Quality Using Cadence Front-End Technologies09 Jul 2010: Cadence Announces Second Quarter 2010 Financial Results Webcast07 Jul 2010: Adoption of Cadence C-to-Silicon Compiler Accelerates in Japan
June
30 Jun 2010: SiS Adopts Cadence Technologies for Advanced SoC Designs21 Jun 2010: Cadence Global Services Enables Industry's First TD-LTE Baseband Chip from Innofidei17 Jun 2010: Cadence Completes Acquisition of Denali11 Jun 2010: Cadence Kick-Starts UVM Adoption with Open-Source Reference Flow Contribution to UVM World11 Jun 2010: Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.011 Jun 2010: Cadence Delivers Extensive Support for TSMC Analog/Mixed-Signal Reference Flow 1.0 for 28nm Process10 Jun 2010: Cadence Prices $300 Million Convertible Senior Notes Offering09 Jun 2010: Cadence Announces Intention to Offer $300 Million Convertible Senior Notes09 Jun 2010: Cadence Announces Comprehensive SOI Design Hub02 Jun 2010: Media Advisory: Meet Leading IP Suppliers at DAC During ChipEstimate.com IP Talks!
May
24 May 2010: Cadence and IBM Team to Develop Leading-Edge IP18 May 2010: Cadence Captivates Delegates at CDNLive! EMEA With New EDA360 Vision13 May 2010: Cadence to Acquire Denali12 May 2010: Cadence Corporate Vice President of Investor Relations Jennifer Jordan to Present at the RBC Technology, Media & Communications Conference11 May 2010: Cadence Corporate Vice President of Investor Relations Jennifer Jordan to Present at the UBS Global Technology and Services Conference07 May 2010: Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Bank of America U.S. Technology Conference06 May 2010: Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Cowen Technology, Media & Telecom Conference05 May 2010: Cadence Accelerates SoC Realization, Reduces Costs With New Open Integration Platform 05 May 2010: Cadence President and Chief Executive Officer Lip-Bu Tan to Present at the JPMorgan Technology, Media & Telecom Conference03 May 2010: VIA’s Centaur Achieves Significant Benefits Using Cadence Virtuoso Space-Based Router at 65 Nanometers
April
28 Apr 2010: Cadence Reports Q1 2010 Financial Results27 Apr 2010: Cadence Issues Blueprint to Battle ‘Profitability Gap’; Counters Semiconductor Industry’s Greatest Threat26 Apr 2010: Cadence Debuts Verification Computing Platform, Accelerating Time and Improving Quality of System Development21 Apr 2010: Cadence Contributes Technology to Boost Verification of Complex Mixed-Signal Chips13 Apr 2010: LSI Adopts Broad Range of Cadence Mixed Signal Technologies12 Apr 2010: TSMC Expands Cadence Tool Support in Integrated Signoff Flow by Adding Synthesis, Place and Route, and RC Extraction12 Apr 2010: HiSilicon Adopts Cadence Mixed-Signal and Low-Power Technologies09 Apr 2010: Cadence Announces First Quarter 2010 Financial Results Webcast08 Apr 2010: Cadence OrCAD PSpice Technology to be Used by STMicroelectronics to Help its Customers Evaluate Analog and Power ICs07 Apr 2010: CDNLive! EMEA Invites Cadence Customers to Go “Beyond Imagination”
March
31 Mar 2010: ChipEstimate.com Announces New IP Partners30 Mar 2010: Rohde&Schwarz Achieves Higher Quality RFICs with Cadence Virtuoso Accelerated Parallel Simulator29 Mar 2010: Cadence Teams with AcAe to Accelerate Customer Transitions to Allegro PCB Products26 Mar 2010: Cadence President and Chief Executive Officer Lip-Bu Tan to Host Annual Meeting of Stockholders24 Mar 2010: Renesas Cuts Design Time by Half on Large-Scale Consumer SoC by Using Cadence Encounter Technology17 Mar 2010: Energy Micro Uses Cadence Low-Power Solution to Develop its Latest Energy-Efficient Microcontroller16 Mar 2010: Cadence Europe Expands Its Academic Network 01 Mar 2010: Chipsbank Adopts Cadence Incisive Xtreme III System to Boost SoC Verification Performance
Feburary
22 Feb 2010: MEDIA ALERT: Cadence Design Systems, Inc. President and CEO Lip-Bu Tan to Ring the NASDAQ Stock Market Opening Bell12 Feb 2010: Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present At The Morgan Stanley Technology, Media & Telecom Conference05 Feb 2010: Cadence Hosts 2010 Investor and Analyst Conference Webcast03 Feb 2010: Cadence Reports Q4 and Fiscal Year 2009 Financial Results01 Feb 2010: Cadence Encounter Digital Implementation System 9.1 Addresses Industry Productivity Crisis for Complex System-on-Chip Design01 Feb 2010: austriamicrosystems Expands Reliance on Cadence Technology to Achieve Seamless Mixed-Signal SoC Designs
January
28 Jan 2010: Cadence Software Validated on STARC QA Database to Help STARC Members Ensure Advanced Chip Design Quality26 Jan 2010: Renesas Adopts Cadence Virtuoso Technology for Mixed-Signal and Analog Design at its Global Design Centers25 Jan 2010: Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric25 Jan 2010: NEC Electronics Adopts Cadence Encounter Digital Implementation System for Leading-Edge 40-nm ASIC Designs08 Jan 2010: Cadence Announces Fourth Quarter And Fiscal Year 2009 Financial Results Webcast
 
케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
전화번호: 031-728-3111(代)
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