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  Trainings & Workshops
Digital IC

Logic Equivalence Checking with Encounter Conformal – Basic & Advanced
July 12, 2007 – July 13, 2007
Cadence Bangalore Office

Voltage Storm Power Rail Analysis
July 23, 2007 – July 25, 2007
Cadence Bangalore Office

CeltIC Nanometer Delay Calculator (NDC)
July 31, 2007
Cadence Bangalore Office
Logic Equivalence Checking with Encounter Conformal – Basic & Advanced
August 16, 2007 – August 17, 2007
Cadence Bangalore Office

SOC Encounter
August 29, 2007 – August 31, 2007
Cadence Bangalore Office

Voltage Storm Power Rail Analysis
September 12, 2007 – September 14, 2007
Cadence Bangalore Office

CeltIC Nanometer Delay Calculator (NDC)
September 24, 2007
Cadence Bangalore Office

Logic Equivalence Checking with Encounter Conformal – Basic & Advanced
September 25, 2007 – September 26, 2007
Cadence Bangalore Office

Custom IC

OA Migration
August 1, 2007 – August 2, 2007
Cadence Bangalore Office

IC 6.1 ADE / VLS
August 6, 2007 – August 10, 2007
Cadence Bangalore Office

Virtuoso AMS Designer
September 6, 2007 – September 7, 2007
Cadence Bangalore office

Virtuoso UltraSim Full–Chip Simulator
September 10, 2007 – September 11, 2007
Cadence Bangalore Office

Verification

Specman Elite Basic Training
July 16, 2007 – July 18, 2007
Cadence Bangalore Office Trainer: Prof. Pravin Dakhole

Advanced SystemVerilog Language
July 25, 2007 – July 27, 2007
Cadence Bangalore Office

Advanced Specman Training
August 6, 2007 – August 8, 2007
Cadence Bangalore Office Trainer: Prof. Pravin Dakhole

Incisive Simulation (IUS)
August 23, 2007 – August 24, 2007
Cadence Bangalore Office

Incisive Simulator Assertion Based Verification (ABV) Using PSL
August 30, 2007
Cadence Bangalore Office

Specman Elite Basic Training
September 10, 2007 – September 12, 2007
Cadence Bangalore Office Trainer: Prof. Pravin Dakhole

Incisive Comprehensive Coverage (ICC)
September 19, 2007 Cadence Bangalore Office

Basic SystemVerilog Language
September 26, 2007 – September 28, 2007
Cadence Bangalore Office

Silicon Package Board

Allegro PCB Editor SKILL Programming Language
August 13, 2007 – August 14, 2007
Cadence Bangalore Office

Allegro PCB Editor Advanced Techniques
October 4, 2007 – October 5, 2007
Cadence Bangalore Office

Allegro PCB SI Foundations
December 17, 2007 – December 19, 2007
Cadence Bangalore Office

  Feedback
We’d like to hear your comments or questions about this newsletter. Email us»


Greetings from Cadence!

Call for Papers for CDNLive! India is still open! Send your abstract to Madhavi Rao.

I’d like to highlight that we have a Sourcelink contest running and encourage you to participate (winners of the June contest are mentioned below). It’s easy - all you have to do is file your service requests through Sourcelink rather than by phone or email. SourceLink is an online knowledge base that answers all your technical questions. SourceLink is available to Cadence Maintenance customers at http://sourcelink.cadence.com.

Rahul Arya
Marketing Director
    Cadence Encounter Digital IC Platform News
Tensilica Enhances Reference Flow With Cadence Encounter RTL Compiler
Cadence Technologies Reduce Area and Power and Ensure Quality Implementation for Tensilica Embedded Cores More»
AMI Semiconductor Successfully Tapes Out Design Using Conformal Constraint Designer for Constraint Signoff
Cadence Encounter Conformal Constraint Designer Adopted By AMIS Semiconductor For ASIC Flow More»
Interview: Logic Designers Expand Horizons
June 4, 2007, Nimish Modi – Cadence Design Systems

Interview describing the Cadence Logic Design Team Solution–a cross–divisional effort that covers all of the technologies from the Encounter and Incisive platforms relevant to logic design More»
Top
    Cadence Incisive Verification Platform News
Realtek Achieves Low-power Functional Closure Using Cadence Logic Design Team Solution
Solution Enables Low–Power Aware Verification Leveraging the Common Power Format More»
Methods To Improve Verification Quality On The Module Level
June 15, 2007, Markus Gross – Siemens AG

Winner of the Best Paper Award in Functional Verification at CDNLive! EMEA, discusses the Siemens AG Plan–to–Closure Methodology. More»
UltraSPARC Processor Emulation Verification: Getting HW/SW Right The First Time
June 5, 2007, Jai Kumar – Sun Microsystems

Emulation steps in to take on challenges of running long directed, random self–checking and DFT diagnostics just where traditional SW simulators run out of gas. More»
Top
    Cadence Virtuoso Custom IC Platform News
Virtuoso NeoCircuit & NeoCircuit DFVirtuoso DFM: Circuit Sizing and Optimization
Irshad Alam, Sr Sales Application Engineer, Cadence Design Systems, India.

Analog Circuit design suffers with a bottleneck of manual cell–level design to achieve the Performance. More»

TSMC And Cadence Collaborate On 65-Nanometer Design Flow For Wireless Designs
Collaboration Combines TSMC Process Technology and Cadence Analog and RF Methodology for Successful RF/SoC Design More»

Virtuoso Multi-Mode Simulation 6.2 Improves Mixed-Signal Verification
May 15, 2007, Dr. Bruce W. McGaughy – Cadence Design Systems
At CDNLive! EMEA 2007 Cadence announced the release of Virtuoso Multi–Mode Simulation 6.2. In this interview Dr. McGaughy discusses the new release. More»
Top
    Cadence Allegro SPB Platform News
Memory Design Considerations When Migrating To DDR3 Interfaces From DDR2
June 7, 2007, Raj Mahajan – MemCore, Inc

This paper from DesignCon 2007 reviews the new DDR3 features and compares and contrasts them to previous features available in the DDR2 specification. More»
Signals On Serial Links: Now You See ’em, Now You Don’t. What Can We Do?
May 29, 2007, Donald Telian – Consultant

A DesignCon2007 panel discussed the problem of un–measurable signals on next–generation serial links. Following are Donald Telian’s observations from the show More»
Cisco’s Michael Umina Tests New PCB Global Routing Technology
May 15, 2007, Michael Umina – Cisco Systems

Michael Umina discusses his initial work with the soon–to–be released Global Route Environment Technology for Allegro PCB design. More»
Top

Congratulations to the winners of the June 2007
Sourcelink promotion!

   Chetan Kappe                           Rambus
   Girish T P
NXP
   Prajapathy Raman
Philips
   Anand Paliwal
HCL Technologies
   Sourabh Vaid
Freescale Semiconductor
Submit your service request on Sourcelink
and be in a draw to win a prize from Cadence!
The more requests you submit, the more chances of your winning!