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  Trainings & Workshops
Digital IC

SOC Encounter
June 25, 2007 - June 27, 2007
Cadence Bangalore Office

Logic Equivalence Checking with Encounter Conformal - Basic & Advanced
June 28, 2007 - June 29, 2007
Cadence Bangalore Office

Fire&Ice QXC Gate level Extraction - EXT511
July 6, 2007
Cadence Bangalore Office

Logic Equivalence Checking with Encounter Conformal - Basic & Advanced
July 12, 2007 - July 13, 2007
Cadence Bangalore Office

Voltage Storm Power Rail Analysis
July 23, 2007 - July 25, 2007
Cadence Bangalore Office

CeltIC Nanometer Delay Calculator (NDC)
July 31, 2007
Cadence Bangalore Office

Custom IC

SKILL Programming for IC Layout Design
June 11, 2007 - June 12, 2007
Cadence Bangalore Office

Advance Spectre
June 14, 2007 - June 15, 2007
Cadence Bangalore Office

Virtuoso Analog Design Environment
July 2, 2007 - July 5, 2007
Cadence Bangalore Office

Virtuoso XL Layout Editor
July 9, 2007 - July 11, 2007
Cadence Bangalore Office

OA Migration
August 1, 2007 - August 2, 2007
Cadence Bangalore Office

IC 6.1 ADE / VLS
August 6, 2007 - August 10, 2007
Cadence Bangalore Office

Verification

Incisive Simulator Assertion Based Verification (ABV) Using PSL
June 19, 2007
Cadence Bangalore Office

Incisive Comprehensive Coverage (ICC)
June 22, 2007
Cadence Bangalore Office

Specman Elite Basic Training
July 16, 2007 - July 18, 2007
Cadence Bangalore Office
Trainer: Prof. Pravin Dakhole

Advanced SystemVerilog Language
July 25, 2007 - July 27, 2007
Cadence Bangalore Office

Advanced Specman Training
August 6, 2007 - August 8, 2007
Cadence Bangalore Office
Trainer: Prof. Pravin Dakhole

Silicon Package Board

Allegro PCB SI Foundations
June 13, 2007 - June 15, 2007
Cadence Bangalore Office

Allegro PCB Editor SKILL Programming Language
August 13, 2007 - August 14, 2007
Cadence Bangalore Office

Allegro PCB Editor Advanced Techniques
October 4, 2007 - October 5, 2007
Cadence Bangalore Office

Allegro PCB SI Foundations
December 17, 2007 - December 19, 2007
Cadence Bangalore Office

  Feedback
We’d like to hear your comments or questions about this newsletter. Email us»

Greetings from Cadence!

The recently concluded Technology on Tour 2007 was a great success! Highlights included a keynote address by Jaswinder Ahuja, Corporate Vice President and Managing Director of Cadence Design Systems India, on "Design Enables the ‘New’ Electronics Ecosystem" and special sessions on RF kits and Cadence Logic Design solution.

We are pleased to announce that the Call for Papers for CDNLive! India 2007, scheduled for October 11 & 12, is still open! It’s a great opportunity to exchange ideas; network with industry experts & other power users of Cadence® technology. If you wish to share your expertise, click on the banner below to submit your abstract. The Call for Papers closes on July 20, 2007. Look forward to seeing your abstracts!

Rahul Arya
Marketing Director

    Cadence Encounter Digital IC Platform News
Cadence QRC Extraction Tool First To Qualify On Tsmc's 45nm Process Technology
Provides silicon-accurate parasitic extraction with high performance for 45nm designs More»
Cadence And Denali Team Up To Enable Advanced DDR-PHY Methodology
Industry’s Most Advanced DDR-PHY Solutions Achieved With Denali’s Databahn PHY Architecture and CPF-Enabled Cadence SoC Encounter and Encounter Timing System More»
Starc To Develop Low-power ‘Pride’ Reference Flow Using Common Power Format
STARC Validates Common Power Format With Design, Verification and Implementation Technologies from Cadence More»
Handling Design Variability Through Encounter SSTA
April 30, 2007, Parveen Khurana - Cadence Design Systems
Describes the rationale behind using SSTA, SSTA modeling requirements and Cadence’s SSTA solution (Encounter SSTA). More»
Top
    Cadence Incisive Verification Platform News
Cadence Improves Logic Designer Productivity Through Enhanced Design-with-verification Flow

Cadence Logic Design Team Solution Minimizes Verification Bottlenecks, Reduces Verification Time, Increases First-Time Silicon Success Rates More»

Fujitsu Kyushu Network Technologies Selects Cadence Systemverilog To Ease Designer Adoption

Incisive Plan-to-Closure Methodology Delivers Advanced SystemVerilog Verification Capabilities to Design Teams, including Test Generation, Checking, and Coverage More»

QLogic Depends on Verification for First-time Silicon Success
May 10, 2007, Tom Paulson - Qlogic

Tom Paulson, principal engineer for QLogic’s system simulation in the Switch Products Group, talked to cdnusers about his challenges, methodology, and verification process for their complex chips. More»
Top
    Cadence Virtuoso Custom IC Platform News
Cadence Accelerates 45-nm Design With TSMC Reference Flow 8.0
New Features Address Design Challenges at 45-nm Node

Cadence Design Systems, Inc. (NASDAQ: CDNS) and Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today announced that Cadence® is providing key capabilities to TSMC Reference Flow 8.0. More»

Disinherited Connections
April 25, 2007, James Roberts - Qualcomm

Explores the next level of multi-rail methodology, doing away with netSet properties and reverting back to explicit pin connections; yet retaining the transparency and automation which inherited connections offered. More»

Constraint Driven Custom Design in IC6.1.0
April 30, 2007, Karun Sharma - Cadence Design Systems

With the release of IC6.1.0 the full custom circuit design methodology received a makeover. This paper discusses the new front-to-back constraint driven design methodology unveiled by IC6.1.0. More»
Top
    Cadence Allegro SPB Platform News
Cadence speeds RF printed-circuit-board design cycle with new allegro PCB technology

Targets Customer’s Design Challenges in High-Frequency and Wireless Applications More»

Comparison of Signaling and Equalization Schemes in High Speed SerDes (10-25Gbps)
April 13, 2007, Dr. Cathy Ye Liu - LSI Logic

This DesignCon 2007 paper compares performance of a variety of signaling and equalization schemes in the SerDes system at speeds of 6Gbps, 10Gbps and higher. More»

Case study of PCI Express Design Simulation using IBIS 4.1
April 25 2007, Nirmal Jain - Rambus

New modeling techniques available in the IBIS 4.1 specification allow for new standard techniques to represent multi-gigabit IO without requiring transistor-level or AMS modeling components. More»
Top

Congratulations to the winners of the May 2007
Sourcelink promotion!

   Jeevan Kharadkar
Conexant Systems
   Girish T P
NXP
   Kalyana Chakravarthy
Qualcore Logic
   Hiram Prasanna Samuel
Gda Technologies
   Aji Varghese
Texas Instruments
Submit your request on Sourcelink and be in a draw to win a prize from Cadence! The more requests you submit, the more chances of your winning!