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April 23, 2007 - April 25, 2007
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Logic Equivalence Checking with Encounter Conformal - Basic & Advanced
April 26, 2007 - April 27, 2007
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April 11, 2007
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Greetings from Cadence !

Welcome to this first edition of the Cadence India eNewsletter. In an effort to make this newsletter as efficient and informative as possible, we have migrated to the new email version. The objective of the eNewsletter is to inform you about the latest updates in Cadence technology and news by platform. Tell us what you think of it by emailing Madhavi Rao (rmadhavi@cadence.com).

Watch out for Cadence Technology on Tour India coming up in May! Details will be on our website shortly.

We look forward to your continued support and suggestions.

Rahul Arya
Marketing Director
  • Functional Verification of Low-power Designs - Low power is definitely the flavor of the year. Why? Primarily because irrespective of which segment you cater to, power consumption is becoming significant concern for your customers. Simple power saving techniques like clock gating has been used for ages, but most significant savings are achieved when advanced power saving structures like PSO and MSV are used. More>>
  • Formal Verification IP (FVIP)- Over the years formal verification has matured significantly. Use of Assertion Based Verification using PSL and SVA has become mainstream. Cadence now has Formal Verification IP's (FVIPs) for AHB, AXI and OCP protocols. More>>
  • EZ Start SystemVerilog Tutorials - Cadence has released new tutorials that can help you get started with writing testbenches in SystemVerilog quickly. These tutorials have downloadable code examples along with documentation explaining the use of SystemVerilog constructs. You can download them free of cost and practice at your own pace.
  • All About Aborts - article by Prashanth Mallikarjun, Lead Sales Application Engineer, Cadence Design Systems (I) Pvt Ltd. This article talks about Aborts in Equivalency checking tool mean inconclusive results. Limitations in formal verification cause aborts. Read Lead Sales AE Prashanth Mallikarjun's article on "All About Aborts" to understand the key causes and solutions for aborts. More>>
  • The Effective Current Source Model(ECSM) is an accurate delay model designed to solve a key industry problem-how to accurately model delay under different voltage scenarios. This is particurlarly problematic for low-power designs. More>>
  • The Cadence Low Power Solution is the industry's first complete flow that integrates logic design, verification, and implementation technologies with the Si2-approved Common Power Format (CPF). Using this comprehensive approach to low-power design, teams can improve productivity, reduce risk, and achieve superior trade-off among timing, power, and area requirements.


  • What's your Power IQ? Take the Test...
  • All gain, little pain. Find out how easy it is to adopt the new Virtuoso platformand realize the many advanced capabilities it provides you. With enhancements to constraint management and advanced device modeling, your job will be easier with measurably better results. And since it's built on an OpenAccess database, you'll quickly benefit from the latest custom design technologies.
  • Get the latest news and find out how other Allegro users reduce costs and accelerate time to market by enabling a constraint-driven collaborative design across IC, package, and PCB domains
  • Attention Allegro Design Entry HDL customers: discover how to convert schematics to content-rich Adobe Portable Document Format (PDF) files. More >>
  • Design-in IP portfolio for memory designs shaves weeks off DDR2 interface design time. Technology leverages IP from Altera and Micron. Now available for download>>