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September 2012

Silicon Realization News
(Custom / Analog, Digital IC, Functional Verification, PCB & IC Packaging, Front End Design)

In the News
Functional Verification - UVM Testflow Phases, Reset and Sequences
Functional Verification - What Does it Take to Migrate from e to UVMe?
Custom IC - Mixed-Signal Methodology Guide Authors Speak Out
Custom IC - Hierarchical Net Cross-Probing - ASIC Layout Hierarchical Net Probing
Custom IC - Simplifying inclusion of RLC (Package/Board) models using custom connect module in (RTL + Spice) AMS Simulations
Encounter Digital - Simple Steps to Debug DRC Violations Undetected in EDI System
PCB & IC Packaging - What's Good About ADW’s Flow Manager? Check out the 16.5 Release and See!
PCB & IC Packaging - What's Good About DEHDL’s Find Functionality? The Secret's in the 16.5 Release!
Virtuoso - SKILL for the Skilled: Many Ways to Sum a List (Part 1)
Virtuoso - SKILL for the Skilled: Many Ways to Sum a List (Part 2)
Virtuoso - Digital Logic in Analog Block – How Will You Test It?
Virtuoso - Things You Didn't Know About Virtuoso: The (Setup) State of Things

SoC Realization News

In the News
Cadence Announces Industry’s First DDR4 Design IP Solutions Are Now Proven in 28nm Silicon
Cadence Executives Offer Insight on Memory Trends Impacting Cloud Computing and Mobility at MemCon 2012
Samsung Speeds SoC-Level Validation Using Cadence Accelerated Verification IP

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