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Cadence
May 2012
Corporate News and Events

In the News
Fujitsu Semiconductor Adopts Cadence Chip Planning System for MCU Chips at Its Design Centers Worldwide

Silicon Realization News
(Custom / Analog, Digital IC, Functional Verification, PCB & IC Packaging, Front End Design)

In the News
Digital - Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology
Digital - Netronome Reaps Significant Power, Performance and Area Benefits with Cadence Encounter Digital Technology
Custom IC - Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
PCB & IC Packaging - What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements!
Low Power Verification - Low-Power Design? Brian Bailey Gets It

Collateral
Digital - Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory
Digital - Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test
Functional Verification - UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

Videos
Formal Verification - Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal Verifier

Communities and Blogs
Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox

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