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February 2012
Corporate News and Events
Cadence Collaborates with Samsung Foundry to Deliver Design-for-Manufacturing Solution for 32-, 28- and 20-Nanometer Chip Design

Silicon Realization News
(Custom / Analog, Digital IC, Functional Verification, PCB & IC Packaging, Front End Design)

Communities and Blogs
Custom / Analog - Customer, Partner DFM Concerns Spur New Methodologies
Custom / Analog - Custom / Analog - Things You Didn't Know About Virtuoso: Measurements Across Corners
Digital - Five-Minute Tutorial: Multiple View-Only Windows In EDI
Verification - Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements
Verification - Video Killed The Reference Manual Star
Verification - Cadence Publishes Definitive Book on Advanced Verification for Today's ICs
Mixed Signal - Panelists: Bridging the Gap Between Analog and Digital Design
Mixed Signal - Power-Aware Mixed-Signal Verification
Low Power - Does Substrate Biasing Have a Future?
Low Power - What’s Next in Low Power

White Paper
Digital - Clock Current Optimization
Verification - Verification Performance is More Than Raw Simulation Speed

SoC Realization News

Verification IP - Try VIP Software at your Desktop

Communities and Blogs
Design IP - JEDEC Mobile Memory Summit: The pace quickens and memory standards must keep up
Design IP - Do you know the new lessons that SSDs are teaching us?

System Realization News

In the News
PCB Design - All the Signal Integrity You Can Shake A Stick At
PCB Design - Watch out SSDs, here comes the NVM Express!

Communities and Blogs
HW / SW Platforms - Creating the Zynq Virtual Platform, Including Errata
HW / SW Platforms - System-Level Design and the Waves of EDA
PCB Design - What's Good About APD’s Die Abstract Libraries? You’ll Need the 16.5 Release to See!
PCB Design - What's Good About PCB SI Signal Integrity Application Mode? It’s in the 16.5 Release!

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