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November 2011
Corporate News and Events
External News
ARM, Cadence, TSMC partner on 20nm design
Cadence collaborates with partners in offering complete EDA software chain

At your desktop: Technology on Tour On-Demand

Silicon Realization News
(Custom IC, Digital IC, Functional Verification, PCB & IC Packaging, Front End Design)

In the News
Custom/Analog - Cadence Library Characterization Scripts Now Available in New TSMC Reference Kit
Low Power - Experts At The Table: Mobile Design Challenges
Digital - Samsung and Cadence Announce Production of Breakthrough 32nm HD Digital Camera SoC for Ambarella
Digital - Samsung, Cadence tout collaboration on SoC
Functional Verification - Importance of Multicore SW Verification Plans

Communities and Blogs
Functional Verification - Verification and the Need for Collaboration
PCB Design - What's Good About PCB SI IOCell Editor in Model Editor? 16.5 Has a Few New Enhancements!
Low Power - Si2 Conference: New Directions for Low-Power Standards
Low Power - Si2 Interoperability Guide V2.0 Available for Download

IC Packaging/SiP - Cadence Low Power Guru Wins Si2’s Distinguished Service Award
Mixed Signal - How Fred Discovered Mixed-Signal Behavioral Modeling

SoC Realization News

Communities and Blogs
Chip Planning - Have your customers "Like" ChipEstimate.com on Facebook for a chance to win a Kindle Fire!

System Realization News

In the News
Functional Verification - Importance of Multicore SW Verification Plans
TLM-Driven Design and Verification - Duolog and Cadence to Validate Interoperability from TLM Virtual Prototype through RTL Assembly
HW and SW Platforms - Xilinx and Cadence Introduce an Extensible Virtual Platform to Enable Software-Centric Approach for Embedded Software Developers
Verification IP - VIP: Behind The Velvet Rope
Verification IP - Atrenta Joins Cadence System Realization Alliance

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