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Cadence
September 2011
Silicon Realization News
(Custom/Analog, Digital IC, Functional Verification, PCB & IC Packaging, Front End Design)

In the News
Custom/Analog - Cadence and GLOBALFOUNDRIES Significantly Speed DFM Signoff. Rambus sees 60x Boost!
Custom/Analog - Cadence is the Exclusive DFM Services Provider for TSMC. What is It?
Custom/Analog - Realizing the Promise of Electrically-Aware Custom IC Design
Low Power - Aren't We Beyond That?
Low Power - Luke Lang's Blog Entry on Low-Power Engineering Community: Hierarchical LP Design 2
Low Power - Sorin Dobre from Qualcomm: Article on UPF/CPFDueling Power Formats
Digital - Samsung 20 nanometer success video
Functional Verification - Ending the Debate - Apples or PC's? e or SystemVerilog?

Collateral
Digital - New White Paper: 20nm Design - How this Advanced Technology Node Will Transform SoCs and EDA

Communities and Blogs
Custom/Analog - SKILL for the Skilled: Introduction to Classes -- Part 2
Digital - GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow
Functional Verification - An Expert’s View on Power Formats and Methodology
Functional Verification - Bringing Static Analysis Methods to Mixed Signal Designs
Functional Verification - Can Your Verification Survive "Boot Camp"?
Functional Verification - DVClub Talk #2: RAM-Resident Database Speeds Verification Coverage Collection
Functional Verification - If Only Carl Friedrich Gauss had IntelliGen in 1850
Functional Verification - UCIS Coverage Standard -- Innovation Means Business
Functional Verification - What Does SystemC Mean for Design and Verification?
Functional Verification - What I Learned Traveling Across the Silicon Prairie
PCB Design - Robert Hanson and Cadence Team Up to Deliver Texas Signal Integrity Event
PCB Design - What's Good About Power Pins in SCM? The Secret's in the 16.5 Release!
PCB Design - What's Good About Up-Reving in DEHDL? You Can Easily Do This in 16.5!
PCB Design - What's Good About Retaining Electrical Constraints? Look to SPB16.5 and See!
Low Power - Ann Mutschler’s Interview with Pete Hardee: Getting the Balance Right

SoC Realization News

In the News
Design IP - Release 4 of DDR3 Serial Presence Detect (SPD) Spec is now available
Design IP - Wide IO's Impact on Memory (Marc Greenberg Interviewed)
Design IP - Will Wide IO Reduce Cache? (Marc Greenberg Interviewed)

Communities and Blogs
Design IP - 3D Thursday: Micron’s 3D Hybrid Memory Cube Delivers More DRAM Bandwidth at Lower Power and in a Smaller Form Factor Using TSVs
Design IP - Yalta in EDA: but Synopsys Ultra Dominant in Interface IP Territory


System Realization News

In the News
TLM-Driven Design and Verification - Sunpuls Technology Adopts Cadence TLM Flow
TLM-Driven Design and Verification - Disappearance of Embedded Design as We Know It
HW and SW Platforms - Webinar: Easing the Pain of FPGA-Based Prototyping

Communities and Blogs
HW and SW Platforms - Virtual Platform UART Use Number 2: Using telnet to Connect to a UART
HW and SW Platforms - Virtual Flash Memory Gets Real
Verification IP - Top 10 Essential System on Chip (SoC) Interfaces
TLM-Driven Design and Verification - IP Cannot be an Efficient Abstraction Level Without SystemC!

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