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August 2011
Silicon Realization News
(Custom IC, Digital IC, Functional Verification, PCB & IC Packaging, Front End Design)

In the News
Low Power    - Going with the Flow by Ed Sperling
Digital            - How Imec and Cadence "Wrapped Up" 3D-IC Test

Communities and Blogs
Custom/Analog             - HiSilicon Boosts Productivity Deploying Advanced Cadence Simulator
20nm Design                - Challenges and Opportunities
Functional Verification  - DVClub: New User Verification Presentations, Upcoming Free Lunches
Functional Verification - More Examples of Missing Real-World Assertions
Functional Verification - Some Reflections on the Development of UVM World
Functional Verification - User View: How to Succeed With Formal Verification
Functional Verification - Video: Discussion with EET’s Brian Fuller on EDA, Engineers, and Social Media
Functional Verification - Video: Open-Silicon CEO Warns of "Exponential Verification Nightmare"
Frontend Design          - What's Good About Retaining Electrical Constraints? Look to SPB16.5 and See!

SoC Realization News

In the News
Design IP - Solving Memory Subsystem Bottlenecks In 3D Stacks

Design IP - Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)

Communities and Blogs
Design IP - Cadence Demonstrates PCIe Gen3 Part 2: Advanced Features

System Realization News

In the News
Cadence Demonstrates Flash Memory Offering at 2011 Flash Memory Summit

Communities and Blogs
HW and SW Platforms - It’s the Software … Unless It’s the Hardware!
TLM-Driven Design and Verification - Creating SystemC TLM-2.0 Peripheral Models

Verification IP - Virtual Flash Memory Gets Real
Verification IP - Cadence - the Broadest Portfolio of Verification IP and Memory Models with Support for All Major Simulators

HW and SW Platforms - Imperas Software Highlights How the Partnership with Cadence is Leveraging the Cadence System Development Suite

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