If you have trouble reading this message, please click here.
July 2011
Corporate News and Events
Cadence Acquires Azuro

Silicon Realization News
(Custom IC, Digital IC, Functional Verification, PCB & IC Packaging, Front End Design)

In the News
Digital - Cadence Encounter Digital Flow Instrumental in Tapeout of Samsung 20-Nanometer Test Chip

Communities and Blogs
Custom/Analog - Q&A: Jim McCanny Discusses Altos Design and Fast IP Characterization
Custom/Analog - Things You Didn't Know About Virtuoso: Viva ViVA!
Custom/Analog - User View: Bringing Digital Control Logic into Analog ICs
Digital - Five-Minute Tutorial: Finding EDI Videos
Digital - User View: A “Structured” Approach to Managing ECOs
Functional Verification - Celebrating the Success of the UVM World Web Site
Functional Verification - More Examples of Missing Real-World Assertions
Functional Verification - True Stories of Assertion Driven Simulation (ADS) in the Wild
Functional Verification - What's Good About Allegro GRE Route Around Etch Shapes? See For Yourself in 16.5!
Mixed Signal - Synchronizing Designs and Behavioral Models in Mixed-Signal Flows
Frontend Design - Cadence Application Packages - New!

SoC Realization News

In the News
TSMC and Cadence DFM Services Collaboration

Communities and Blogs
Design IP - Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon
Design IP - Gabe on EDA: The IP Market Is A Way Out From Business As Usual For EDA Vendors

System Realization News

In the News
HW and SW Platforms - System-Level Design: Virtual Prototyping Takes Off

Verification IP - Cadence VIP Catalog - Broadest Portfolio of  Verification IP and Memory Models for ALL Major Simulators

Communities and Blogs
HW and SW Platforms - Q&A: Linking Virtual Prototypes to High-Level Synthesis

Forward this mail to a friend/colleague | Feedback
For more information, log on to www.cadence.com
Cadence respects your online time and privacy.
To unsubscribe from all future Cadence email communications, Please click here