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Cadence India eNewsletter
Cadence India eNewsletter
Services
  Trainings & Workshops
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  Virtuoso Custom IC Platform
Virtuoso AMS Designer
13 June-15 June
Bangalore, India
 
  Encounter Digital IC Platform
Signoff Timing Analysis With Encounter Timing System
18 April – 19 April 2011
Bangalore, India

Floor Planning, Physical Synthesis, Place And Route
4 May -6 May 2011
Bangalore, India

Logic Equivalence Checking With Encounter Conformal EC
9 May -10 May 2011
Bangalore, India

Encounter Conformal Low-Power Verification With CPF
26 May 2011
Bangalore, India

Floor Planning, Physical Synthesis, Place And Route (FLAT)
6 June-8 June
Bangalore, India

Signoff Timing & SI Analysis With Encounter Timing System
27 June-28 June
Bangalore, India

Encounter RTL Compiler
13 June-14 June
Bangalore, India
 
  Incisive Verification Platform
System Verilog Advanced Verification Using UVM
25 April – 28 April 2011
Bangalore, India

Specman Elite Basics For Verification Environment Users
18 May- 19 May 2011
Bangalore, India

Specman Elite Advanced Verification
30 May- 1 June 2011
Bangalore, India

System Verilog Advanced Verification Using UVM
20 June-23 June
Bangalore, India

 
  Allegro PCB Design Platform
Allegro PCB Editor
11 May - 12 May 2011
Bangalore, India

Allegro PCB SI Foundations
16 May - 17 May 2011
Bangalore, India

Allegro AMS Simulator / PSPICE
1 June-2 June
Bangalore, India

Allegro Design Entry HDL-Foundations
30 June-30 June
Bangalore, India

 
April 2011 
Virtuoso
Custom IC Platform
news
Encounter
Digital IC
Platform
news
Incisive
Verification
Platform
news
Allegro
PCB Design
Platform
news
Cadence Design
& Verification
IP Updates

Cadence Technology on Tour

 
  Virtuoso Custom IC Platform news
Cadence Enhances Unified Custom/Analog Flow to Boost Productivity at Nodes Down to 20nm
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced major enhancements to its Virtuoso®-based custom/analog flow, boosting productivity across the entire flow from initial design...
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EDP Workshop: Will Security Concerns Slow EDA in the Cloud?
Is public cloud computing secure enough for IC design work? Two different perspectives emerged at the IEEE Electronic Design Processes (EDP) workshop April 7-8, where an Intel manager detailed security concerns...
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Virtuoso IC 5.1.41 Was Good but Virtuoso IC 6.1 is Better
With the recent release of unified custom/analog flow that is based on the latest version of the Virtuoso IC 6.1.5 technologies (see Virtuoso IC 6.1.5 press release here), it is time to revisit the strengths of Virtuoso IC 6.1 platform...
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Virtuoso DFM Option
At 45 nanometer technology process, TSMC has added mandatory DFM checks to address the lithography, etch, and mask systematic manufacturing variations that surpass random variations as the prime limiters ...
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  Encounter Digital IC Platform news
How Easy Is It to Switch Off Power?
How easy is it to switch off power? "Honey, could you please make sure all the lights are off before going to bed?" Although I am always wondering why I have to be one to do this...
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Encounter Quick Tip: How to Repair Command Line Navigation When Launching via bsub
When two users report the same issue in the same week I'm glad I can share the problem and solution via this blog....
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  Incisive Verification Platform news
New Enterprise Planner Videos
If a picture is worth a thousand words, then a video must be priceless -- at least I hope you think so. Recently, we created a few improvised videos on how to get started with Enterprise Planner....
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  Allegro PCB Design Platform news
What's Good About Capture CIS Relational Tables? SPB16.3 Has a Few New Enhancements!
If you have defined relational fields in your Allegro Design Entry CIS configuration, you can now include the relation fields in your CIS Bill Materials...
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What's Good About PCB PI Discontinuity Modeling? See For Yourself in SPB16.3!
The current Allegro PCB Power Integrity (PI) tool is fast, but not accurate enough in the high frequency band due to the effect of discontinuities. This feature uses a discontinuity model in the PI analysis...
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  Cadence Design & Verification IP Updates
Cadence Releases Industry’s First Wide I/O Memory Controller IP Solution
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it is first to market with a licensable, wide I/O memory controller core, along with an integration environment, that brings PC-like performance...
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Cadence Announces Availability of World’s First DDR4 IP Solution
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced a comprehensive DDR4 solution that will enable SoC designers to take immediate advantage...
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