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Cadence India eNewsletter
Cadence India eNewsletter
Services
March 2011 
Incisive
Verification
Platform News
Virtuoso
Custom IC
Platform News
Encounter
Digital
IC Platform News
Allegro PCB
Design
Platform news
  Trainings & Workshops
More Information»
 
  Incisive Verification Platform
Incisive Enterprise Simulator
28 March – 29 March 2011
Bangalore, India

System Verilog Advanced Verification Using UVM
25 April – 28 April 2011
Bangalore, India
Specman Elite Basics For Verification Environment Users
18 May- 19 May 2011
Bangalore, India

Specman Elite Advanced Verification
30 May- 1 June 2011
Bangalore, India
 
  Virtuoso Custom IC Platform
Virtuoso AMS Designer
21 March – 23 March 2011
Bangalore, India

SKILL Language Programming
5 April – 8 April 2011
Bangalore, India

Virtuoso Connectivity-Driven Layout
11 April 2011
Bangalore, India

Virtuoso Ultrasim Full-Chip Simulator
18 April - 20 April 2011
Bangalore, India

Skill Programming For IC Layout Design
2 May - 3 May 2011
Bangalore, India

Using Virtuoso Spectre Simulator Effectively
9 May - 10 May 2011
Bangalore, India

IC 6.1.5 Update Workshop
25th Mar, 1st Apr, 15th Apr and 22nd Apr
Bangalore, India
 
  Encounter Digital IC Platform
Floor Planning, Physical Synthesis, Place And Route (Hierarchical)
11 April 2011
Bangalore, India

Signoff Timing Analysis With Encounter Timing System
18 April – 19 April 2011
Bangalore, India

Floor Planning, Physical Synthesis, Place And Route
4 May -6 May 2011
Bangalore, India

Logic Equivalence Checking With Encounter Conformal EC
9 May -10 May 2011
Bangalore, India

Encounter Conformal Low-Power Verification With CPF
26 May 2011
Bangalore, India
 
  Allegro PCB Design Platform
Allegro Design Entry HDL-Foundations
5 April 2011
Bangalore, India

Allegro PCB Editor
11 May - 12 May 2011
Bangalore, India

Allegro PCB SI Foundations
16 May - 17 May 2011
Bangalore, India

 
 
  Incisive Verification Platform news
A Modest Proposal: Using Formal to Close Coverage Gaps
In my last blog post, I summarized some of our activities at DVCon and mentioned briefly the "Birds of a Feather" (BoF) panel and discussion on "Strategies in Verification for Random Test Generation: New Techniques and Technologies" held Monday evening Today I'd like to fill in some of the details of this session and discuss the proposal that I made for a combined solution from Cadence and NextOp Software...
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Broadcom Expands Use of Cadence Verification Computing Platform to Tackle System Realization
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Broadcom Corporation, a global leader in semiconductors for wired and wireless communications, is expanding its use of the Cadence® Verification Computing Platform, Palladium® XP, to help validate its complex system designs before committing them to silicon. ...
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Cadence Opens and Extends Verification IP Catalog for Use Across Silicon, SoC and System Development
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today detailed the extensive expansion of its broad portfolio of verification IP (VIP) and memory models, which delivers a robust verification solution spanning silicon, SoC and system development. The Cadence® VIP offering boasts support of new protocols such as...
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  Virtuoso Custom IC Platform News
Virtuoso IC6.1.5: Software and Fine Red Wine
Software, like fine red wine, can get better with age as well -- but it requires constant advancements to remain a vibrant contributor. Such is the case with the Virtuoso IC6.1.5 custom/analog technology release, which delivers on the promise of Silicon Realization ...
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Analog/Mixed Signal Routing Challenges in Sub-Nanometer Designs
The IC industry is facing several design and manufacturing/yield related challenges as process geometries continue to shrink. With the increased design size and complexity it has become a bottleneck to meet the signal integrity and manufacturing requirements. It is mandatory to address these signal-integrity issues at routing stage...
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IMS CHIPS Standardizes on Cadence Silicon Realization Product Line for Advanced Gate Array Design
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that IMS CHIPS has adopted Cadence® Silicon Realization technologies for its special mixed-signal gate array technology....
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  Encounter Digital IC Platform News
Encounter Puzzler #3 Solution: Renaming a Net Logically
Once again, the Encounter Digital Implementation designer community has stepped up to the challenge. Last week's puzzler -- renaming a net logically in Encounter -- was solved in short order. Let's add J2mh and Sims to the list of Encounter Wizards (along with regular commentator and guest blogger Jason G)....
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28 nm IC Design: The Devil Is In The Details
Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die on a wafer means lower per unit cost...
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  Allegro PCB Design Platform News
What's Good About Capture OLE Object Placing? You Can Easily Do This in SPB16.3!
Object Linking and Embedding (OLE) support in SPB16.3 Allegro Design Entry CIS (or Capture) allows you to embed or link an object on your schematic page. The object types that you are allowed to embed or link are defined by the applications and files available on your computer...
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What's Good About ADW’s Flow Manager? Check Out the ADW16.3 Release and See!
The ADW16.3 Allegro Design Workbench has a desktop cockpit that allows engineers to view their internal design processes and the applications applicable to each of the steps in their flow. The Workbench guides the engineer through the flow and provides a consistent approach to otherwise disparate processes across the entire design team...
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