If you are having trouble reading this newsletter, please click here.
Cadence India eNewsletter
Cadence India eNewsletter
Services
February 2011 
Encounter
Digital Implementation
Platform News
Virtuoso
Custom IC
Platform News
Incisive Verification
Platform News
Allegro PCB
Design
Platform news
  Trainings & Workshops
More Information»
 
  Encounter Digital IC Platform
Encounter Conformal Low-Power Verification With CPF
23 February 2011
Bangalore, India

Encounter RTL Compiler
28 February – 1 March 2011
Bangalore, India

Floor Planning, Physical Synthesis, Place And Route (Hierarchical)
11 April 2011
Bangalore, India

Signoff Timing Analysis With Encounter Timing System
18 April – 19 April 2011
Bangalore, India
 
  Virtuoso Custom IC Platform
Analog modeling with Verilog-A
7 March – 9 March 2011
Bangalore, India

Virtuoso AMS Designer
21 March – 23 March 2011
Bangalore, India

SKILL Language Programming
5 April – 8 April 2011
Bangalore, India
 
  Incisive Verification Platform
Specman Elite Advanced Verification
7 March – 10 March 2011
Bangalore, India

Incisive Enterprise Simulator
28 March – 29 March 2011
Bangalore, India

System Verilog Advanced Verification Using UVM
25 April – 28 April 2011
Bangalore, India
 
  Allegro PCB Platform
Allegro AMS Simulator / PSpice
28 February – 1 March 2011
Bangalore, India

Allegro Design Entry HDL-Foundations
5 April 2011
Bangalore, India
 
 
  Encounter Digital Implementation Platform news
Cadence Drives Giga-gate/Gigahertz Design at 28nm with New Digital End-to-end Flow
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today advanced the design of giga-gate / gigahertz system on chips...
More»

Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow
It hasn't been that long, but do you recall your new year's resolution? Eat healthier? Have more work-life balance? Exercise more? ...
More»
.
New Silicon Realization Design Methodology Boosts 3D ICs With TSVs
Cadence this week (Jan. 31) is announcing a "unified" 3D IC design methodology that drives creation, implementation, and verification...
More»
.
  Virtuoso Custom IC Platform news
Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 1)
There is no doubt in my mind that assertions will play a significant role in analog verification, be it verifying individual analog blocks ...
More»
.
Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 2)
The design and verification methodology for analog circuits has not changed much over the past decade. But the complexity of analog designs...
More»
.
  Incisive Verification Platform news
De-Mystifying SystemC: What is TLM?
In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries...
More»
.
SystemC: It's Neither Complicated Nor Belligerent!
I was recently talking to a customer who was looking to move up in abstraction from RTL to SystemC for all the usual good reasons...
More»
.
  Allegro PCB Design Platform news
What's Good About Capture Locking Objects? The Secret's in the SPB16.3 Release!
The Allegro Design Entry CIS (Capture - Allegro flow) now includes an object locking feature. This feature allows you to temporarily lock and object on your schematic or board...
More»
.
What's Good About Allegro Measure, Grids and Formulas? See For Yourself in SPB16.3!
In the SPB16.3 release, the show measure (Display — Measure) command now measures the separation between any two objects regardless of the layer...
More»
.
For more information log on to www.cadence.co.in
.
Forward this mail to a friend/colleague  | Feedback
Cadence respects your online time and privacy.
To unsubscribe from all future Cadence email communications, Please click here