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Cadence India eNewsletter
Cadence India eNewsletter
Services
November 2010 
Encounter
Digital IC
Platform News
Virtuoso
Custom IC
Platform News
Incisive Verification
Platform News
Allegro SPB
Platform
News
  Trainings & Workshops
More Information»
 
  Digital IC
Floorplanning, Physical Synthesis, Place and Route (Flat) v9.1
30 Nov 2010 - 03 Dec 2010
Bangalore, India

Logic Equivalence Checking with Encounter Conformal EC v9.1
24 Nov 2010 - 26 Nov 2010
Bangalore, India

Signoff Power-Grid Analysis with Encounter Power System v8.1
15 Nov 2010 - 17 Nov 2010
Bangalore, India
 
  Custom IC
Virtuoso XL Layout
Editor v5.1.41
06 Dec 2010 - 08 Dec 2010
Bangalore, India

Virtuoso Advance Spectre vMMSIM7.1 Delivery Method: ILT
23 Nov 2010 - 25 Nov 2010
Bangalore, India
 
  Allegro
Allegro PCB Power Integrity v16.2
23 Nov 2010 - 24 Nov 2010
Bangalore, India
 
 
  Encounter Digital IC Platform News
CDNLive! Silicon Valley 2010: What EDA360 Means to Digital Implementation Engineers
By Robert Dwyer on October 27, 2010
CDNLive! Silicon Valley 2010 -- our user's group meeting and more -- kicked off yesterday morning at the Fairmont Hotel in San Jose, California. It's been 2 years since the last CDNLive! (Last’s event was online-only) where I captured...
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CDNLive! Silicon Valley 2010: User Papers Explore Digital Implementation
By Robert Dwyer on November 4, 2010
I previously wrote about the general session of the 2010 CDNLive! Silicon Valley conference, focusing on what EDA360 means for Digital Implementation engineers. Today I wanted to share a little more about a couple of papers I co-presented along with...
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  Virtuoso Custom IC Platform News
SKILL for the Skilled: Making Programs Clear and Concise
By Jim Newton on November 08, 2010
The SKILL programming language augments Cadence core tool functionality for Virtuoso and Allegro customers. It is also an important development tool for internal Cadence services organizations as well as Cadence product development groups. We see the...
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Things You Didn't Know About Virtuoso: ADE XL--Take This Job and...Run It!
By Stacy Whiteman on October 06, 2010
Sometimes these articles just write themselves... Last week, 3 different people asked me questions about the ADE XL Run Options form. Sadly, the odds that 3 people in the same week would ask a question to which I actually knew the answer are vanishingly...
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  Incisive Verification Platform News
Verification Goldmine: 50 User Papers on Formal, Multi-Engine, and Assertion-Based Verification (ABV)
By Team Verify on November 02, 2010
With all due respect to our Tech Pubs writers, Solutions Architects, and contributors to this blog, nothing beats hearing the experiences of end users applying a given tool or methodology to their real world challenges. Fortunately, Team Verify has been...
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CDNLive! Silicon Valley 2010 in the Rear-View Mirror
By Tom Anderson on November 2, 2010
Well, we all survived another very busy CDNLive! Event last week. Since I posted a preview beforehand I would be remiss if I didn't let you know what happened. The bottom line is that this was a really good show, with more than forty talks covering....
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  Allegro SPB Platform News
What's Good About Allegro Router and Via Changes? SPB16.3 Has a Few New Enhancements!
By Gerald "Jerry" Grzenia on October 20, 2010
This week, I’ll be closing discussions on the new SPB16.3 Allegro PCB Router improvements. The focus is on several enhancements for via support. The Use_Via Rule Many times you need to restrict the usage of specific vias in a region. Allegro PCB...
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A Shorter, Predictable Design Cycle for Complex PCBs -- Electrical Constraint Sets (ECSets)
By Hemant Shah on October 29, 2010
This is the first in a series of blogs focused on how you can make your design cycle predictable and shorter for PCB designs that are increasing in complexity. PCB designers have to deal with increased complexities while design teams are dispersed geographically...
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