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Cadence India eNewsletter
Cadence India eNewsletter
Services
October 2010 
Encounter
Digital IC
Platform News
Virtuoso
Custom IC
Platform News
Incisive Verification
Platform News
Cadence Front End Design News Allegro SPB
Platform
News
  Trainings & Workshops
More Information»
 
  Digital IC
Floorplanning, Physical Synthesis, Place and Route (Hierarchical) v9.1
02 Nov 2010 - 02 Nov 2010
Bangalore, India

Logic Equivalence Checking with Encounter Conformal
EC v9.1
19 Oct 2010 - 20 Oct 2010
Bangalore, India
 
  Custom IC
Analog Modeling with
Verilog-A v6.2
18 Oct 2010 - 20 Oct 2010
Bangalore, India

SKILL Language
Programming v5.1.41
25 Oct 2010 - 28 Oct 2010
Bangalore, India

SKILL Programming for IC Layout Design v5.1.41
02 Nov 2010 - 03 Nov 2010
Bangalore, India
 
  Verification
Specman Elite Advanced Verification v8.1
01 Nov 2010 - 03 Nov 2010
Bangalore, India

SystemVerilog Advanced Verification using OVM v8.2
18 Oct 2010 - 22 Oct 2010
Bangalore, India
 
 
  Encounter Digital IC Platform News
Sunplus Reduces Design Cycle on High-Speed Multi-Million-Gate SoC Using Cadence Encounter Digital Implementation System
SAN JOSE, Calif., 27 Sep 2010
Large-Scale Capacity, Multi-CPU Backplane and Advanced Design Exploration Significantly Boost Designer Productivity for Silicon Realization.
More»

Global Unichip Boosts Design Productivity with Cadence Encounter Timing System
SAN JOSE, Calif., 13 Sep 2010
Integrated Signoff Analysis Helps GUC Reduce Time to Final Design Closure for Faster Silicon Realization.
More»
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  Virtuoso Custom IC Platform News
Introducing Virtuoso Pcell IDE in IC 6.1.4
Debugging Parameterized Cells (Pcells) has historically been a manual task where you load the SKILLcode in the CIW and instantiates a few configurations of the Pcell to verify correctness of the code.If you find any issue in the Pcell geometries, you need to identify the code causing that issue.…
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Now Playing: Custom IC Videos-to-Go
By Stacy Whiteman on September 27, 2010
I wanted to take a brief detour from my usual postings to point out a couple of new delivery mechanisms we're trying out for distributing video collateral -- making better use of some of those toobz on the interwebs. First, we've made some of...
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  Incisive Verification Platform News
"We Want UVM 1.0! When Do We Want it? Now!"
By Adam Sherer on October 7, 2010
Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring...
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Report From The Front Lines Of The Silicon Valley Electronics Industry With AE Darrow Chu
By Joseph Hupcey III on September 27, 2010
Lately the tone of the trade press and blogs about the Silicon Valley electronics industry has been largely positive. For a variety of reasons this is a good thing, but my natural skepticism compelled me to "field check" this data with a high...
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  Allegro SPB Platform News
What's Good About PCB SI DML Path Setting? See For Yourself in the SPB16.3 Release!
By Gerald "Jerry" Grzenia on September 29, 2010
With the SPB16.3 release of Allegro PCB SI , there’s a new methodology for Device Modeling Language (DML) path setting and searching. In previous releases, DML and IML paths were controlled graphically with the Library Browser, as shown below: They...
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What's Good About Allegro GRE Rake Functionality? You’ll Need the SPB16.3 Release to See!
By Gerald "Jerry" Grzenia on September 15, 2010
The SPB16.3 Global Route Environment (GRE) Expanded Rakes functionality provides better visualization of the connectivity of the Bundles. In previous versions, this functionality was only provided when the user moved the gather point. Now this functionality...
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