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Cadence India eNewsletter
Cadence India eNewsletter
Services
September 2010 
Encounter
Digital IC
Platform News
Virtuoso
Custom IC
Platform News
Incisive Verification
Platform News
Cadence Front End Design News Allegro SPB
Platform
News
  Trainings & Workshops
More Information»
 
  Digital IC
Floor planning,
Physical Synthesis,
Place and Route (Flat) v9.1

20 Sep 2010 - 22 Sep 2010
Bangalore, India

Logic Equivalence
Checking with Encounter Conformal EC v9.1

21 Sep 2010 - 22 Sep 2010
Bangalore, India

Encounter RTL Compiler v9.1
06 Oct 2010 - 07 Oct 2010
Bangalore, India
 
  Custom IC
Virtuoso XL Layout Editor V5.1.41
27 Sep 2010 - 29 Sep 2010
Bangalore, India
 
  Verification
Formal Analysis Fundamentals with Incisive Formal Verifier v8.2
14 Sep 2010 - 15 Sep 2010
Bangalore, India

Incisive Simulation of
PSL Assertions v8.2

13 Sep 2010 - 13 Sep 2010
Bangalore, India

Specman Elite Basics for Verification Environment
Users v8.1

20 Sep 2010 - 21 Sep 2010
Bangalore, India

SystemC Language Fundamentals v8.2

04 Oct 2010 - 05 Oct 2010
Bangalore, India
 
 
  Encounter Digital IC Platform News
AppliedMicro™ User Interview – A “Bigger Picture” With EDA360
By Richard Goering on June 9, 2010
Applied Micro Circuits Corp. (AMCC) is designing some challenging SoCs for multimedia network applications.
More»
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Webinar: SOI Gives More Performance Per Watt, And There's An Easy Path
By Michael Jacobs on August 20, 2010
If you've seen any of the recent buzz lately around Silicon-On-Insulator (SOI), you'd know that it's an excellent option that can enable you to meet lower power consumption and die area targets without sacrificing performance or functionality.
More»
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  Virtuoso Custom IC Platform News
Things You Didn't Know About Virtuoso: Outputs Setup in ADE XL
By Stacy Whiteman on August 25, 2010
Continuing on our exploration of ADE XL (see here and here for previous articles), today let's take a look at the Outputs area in the center of the screen.
More»
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Analog Design vs. Automation -- Why Are They At Odds?
By Nigel Bleasdale on August 17, 2010
Back in 2002 and 2003 there was a lot of talk about analog synthesis being the "next new thing" to close the productivity gap between analog and digital designers.
More»
  Incisive Verification Platform News
Users Employ Specman Constrained-Random Verification for Complex IP
By Team Specman on September 03, 2010
Two recent customer examples have shown the effectiveness of Specman constrained-random verification for complex SoCs.
More»
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Performance Tips and Tricks: Coding e Ports for Enhanced Performance
By Team Specman on September 03, 2010
This blog entry builds on last week's Tips and Tricks posting in which we discussed the usage of list.delete(0) in Tip 1. This week, we discuss a topic that is close to many users.
More»
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 Cadence Front End Design News
Andes Technology Adopts Cadence Digital Front-End Low-Power Flow
SAN JOSE, Calif. and TAIPEI, Taiwan, 30 Aug 2010
Andes Deploys the Common Power Format and Cadence Digital Solution to Provide Its Customers a Scalable, Configurable Low-Power Management Framework.
More»
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  Allegro SPB Platform News
What's Good About Capture Objects Look and Feel? You Can Change Them in SPB16.3!
By Gerald "Jerry" Grzenia on August 25, 2010
The SPB16.3 release of Allegro Design Entry CIS (known as Capture) has some cool new features!
More»
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What's Good About Deleting Parts in ADW? You Can Easily Do This In ADW16.3!
By Gerald "Jerry" Grzenia on August 18, 2010
Part, Schematic, Footprint and Models can all be deleted from the database now with the Allegro Design Workbench ADW16.3 release.
More»
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