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Cadence India eNewsletter
Cadence India eNewsletter
Services
August 2010 
Encounter
Digital IC
Platform News
Virtuoso
Custom IC
Platform News
Incisive Verification
Platform News
Cadence Front End Design News Allegro SPB
Platform
News
  Trainings & Workshops
More Information»
 
  Digital IC
CPF Covering Conformal Low Power- V9.1 11 Aug 2010 - 11 Aug 2010 Bangalore, India

Signoff Timing Analysis with Encounter Timing System v8.1 12 Aug 2010 - 13 Aug 2010 Bangalore, India

Virtuoso Platform Update Training: Physical Design IC6.1 v6.1.3 18 Aug 2010 - 18 Aug 2010 Bangalore, India

Logic Equivalence Checking with Encounter Conformal EC v9.1 26 Aug 2010 - 27 Aug 2010 Bangalore, India
 
  Custom IC
Virtuoso Advance Spectre vMMSIM7.1 07 Sep 2010 - 08 Sep 2010 Bangalore, India
 
  Verification
SystemVerilog Advanced Verification using OVM v8.2 16 Aug 2010 - 20 Aug 2010 Bangalore, India
 
  Allegro
Allegro PCB Editor Advanced Techniques v16.3 06 Sep 2010 - 06 Sep 2010 Bangalore, India

Allegro PCB Router Basics v16.01 19 Aug 2010 - 20 Aug 2010 Bangalore, India
 
 
  Encounter Digital IC Platform News
Realtek Semiconductor Selects Cadence Design Systems as its Strategic EDA Solutions Provider
Holistic Design and Verification Solutions Drive Realtek’s Innovation and Reduce Time to Market for Communications Network ICs.
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Programatically Capturing Cell Delay In The Encounter Digital Implementation System
By Robert Dwyer on July 23, 2010
A while back we were talking about how to programatically troubleshoot timing violations in Encounter.
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  Virtuoso Custom IC Platform News
Things You Didn't Know About Virtuoso: ADE XL Test Setup
By Stacy Whiteman on August 5, 2010
In my last post, I left you in suspense, with your mouse hovering over the words "Click to add test" in ADE XL.
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Fast and Accurate Sensitivity-Based-Multi-Corner Extraction
Girraj Khandelwal, Custom IC Technical Field Operations, Cadence Design Systems
Semiconductor process technology has been continually scaling down for the past four decades and the trend continues.
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  Incisive Verification Platform News
Hitachi Achieves 10,000 Times Performance Boost Using Cadence Technology to Verify Complex Design
Design Teams Speed System Realization with Transaction-Based Acceleration Methodology, C-to-Silicon Compiler and Palladium III Acceleration/Emulation System.
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Hitachi Raises System-Level Simulation Performance 100x with Cadence Palladium Transaction-Based Acceleration
Cadence Verification Acceleration Technology Compresses Network System Verification Schedules and Boosts Quality and Reliability.
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 Cadence Front End Design News
Casio Cuts Design Cycle Time and Improves Quality Using Cadence Front-End Technologies
Cadence High-Level Synthesis and Logic Verification Help Casio Develop New Graphics Processor for Next-Generation Digital Cameras.
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Fujitsu Adopts Cadence Encounter Conformal ECO Designer
Software Helps Reduce Total Design Time and Costs in Engineering Change Order Implementation Flow.
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  Allegro SPB Platform News
Cadence Develops Die Model Enabling Comprehensive Chip-Package Co-Design Solution with Fujitsu
Solution Uses Encounter Power System and Allegro Package Designer to Implement Standard Format for Die Models, Enabling Accurate Package ASIC/MCU Analysis.
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What's Good About The PCB SI Model Editor? See For Yourself In The SPB16.3 Release!
By Gerald "Jerry" Grzenia on August 4, 2010
With the SPB16.3 release of PCB SI, the Model Editor has been added to allow you to view, update, and check the syntax and data integrity for various models.
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For more information log on to www.cadence.co.in
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