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Cadence India eNewsletter
Cadence India eNewsletter
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July 2010 
Cadence Encounter
Digital IC
Platform News
Cadence Virtuoso
Custom IC
Platform News
Cadence Incisive Verification
Platform News
Cadence Allegro SPB
Platform News
  Trainings & Workshops
More Information»
 
  Digital IC
Floorplanning, Physical Synthesis, Place and Route (Flat) v9.1
21 Jul 2010 - 23 Jul 2010
Bangalore, India

Logic Equivalence Checking with Encounter Conformal
EC v9.1
22 Jul 2010 - 23 Jul 2010
Bangalore, India
 
  Custom IC
Analog Modeling with Verilog-A v6.2 09 Aug 2010 - 11 Aug 2010
Bangalore, India

SKILL Language Programming v5.1.41
19 Jul 2010 - 22 Jul 2010
Bangalore, India

SKILL Programming for IC Layout Design v5.1.41
26 Jul 2010 - 27 Jul 2010
Bangalore, India
 
  Verification
Specman Elite Advanced Verification v8.1
02 Aug 2010 - 04 Aug 2010
Bangalore, India

SystemC Language Fundamentals v8.2
12 Jul 2010 - 13 Jul 2010
Bangalore, India

System Verilog Advanced Verification using OVM v8.2
26 Jul 2010 - 30 Jul 2010
Bangalore, India
 
  Allegro
Allegro Design Entry HDL: Foundations v16.2
12 Jul 2010 - 12 Jul 2010
Bangalore, India
 
 
CDNLive! India 2010 – Call for Papers Now Open!
  Encounter Digital IC Platform News
DAC 2010 - A “Coming Out” Party For 3D-IC Design
By Rahul Deokar on June 28, 2010
Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor faces were not long and serious, but more purposeful and forward-looking.
More»
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Mixed Signal: Why The Sudden Attention?
By Peter McCrorie on May 24, 2010
With DAC 2010 rapidly approaching, we can again expect that lots of EDA and IP vendors will use “mixed signal” somewhere in their company’s messaging.
More»
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  Virtuoso Custom IC Platform News
ARM And Cadence Get To The “Core” Of Mixed-Signal Design
By Mladen Nizic on June 8, 2010
An increasing number of analog and mixed-signal designs in automotive, power management, wireless, medical, and industrial applications require digital control.
More»
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Video Demo: Your Maiden Voyage Across OCEAN
By Samir Jafferali on March 29, 2010
I still remember my first encounter with OCEAN. It was 2002 and my
co-worker had asked me to run a simple test for him.
More»
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Netlist Based IR Drop and Electromigration Analysis Flow in Virtuoso® UltraSim®
By Irshad Alam
With CMOS process technology scaling down to 65nm and below, IR-drop and electromigration (EM) effects become significant design considerations in the arena of VLSI Design.
More»
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  Incisive Verification Platform News
SiS Adopts Cadence Technologies for Advanced SoC Designs
Deployment of Cadence Verification, Digital and Custom/Analog Technologies and Methodologies to Help Boost Productivity and Profitability.
More»
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Why The UVM Is Ready For Production Use Today - Part 2
By Tom Anderson on July 1, 2010
In my last blog post, I talked about the three most common questions I heard at DAC from people who had some concerns about moving to the Universal Verification Methodology (UVM).
More»
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  Allegro SPB Platform News
What's Good About Via DRCs In Allegro Constraint Manager? It's In SPB16.3!
By Gerald "Jerry" Grzenia on July 2, 2010
Current design technologies require extremely tight matching requirements right down to the overall net topologies to ensure that any deviations in propagation delays are minimized.
More»
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What's Good About Vias And The Allegro Router? SPB16.3 Has A Few New Enhancements!
By Gerald "Jerry" Grzenia on June 22, 2010
A few new enhancements specific to vias in the SPB16.3 release of Allegro PCB Editor have been introduced.
More»
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