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Cadence India eNewsletter
Cadence India eNewsletter
Services
June 2010 
Cadence Encounter
Digital IC
Platform News
Cadence Virtuoso
Custom IC
Platform News
Cadence Incisive Verification
Platform News
Cadence Allegro SPB
Platform News
   
Cadence and IBM Team to Develop Leading-Edge IP
 
  Trainings & Workshops
More Information»
 
  Digital IC
Encounter RTL Compiler v9.1
07 Jul 2010-08 Jul 2010
Bangalore, India

Floorplanning, Physical Synthesis, Place and Route (Flat) v9.1
14 Jun 2010-16 Jun 2010
Bangalore, India

Logic Equivalence Checking with Encounter Conformal
EC v9.1
21 Jun 2010 - 22 Jun 2010
Bangalore, India
 
  Custom IC
Virtuoso XL Layout Editor v5.1.41
16 Jun 2010-18 Jun 2010
Bangalore, India
 
  Verification
Specman Elite Basics for Verification Environment Users v8.1
10 Jun 2010-11 Jun 2010
Bangalore, India

SystemVerilog Advanced Verification using OVM v8.2
14 Jun 2010-18 Jun 2010
Bangalore, India
 
  Allegro
Allegro Design Entry HDL: Foundations v16.2
12 Jul 2010-12 Jul 2010 Bangalore, India
 
 
CDNLive! India 2010 – Call for Papers Now Open!
  Encounter Digital IC Platform News
Mixed Signal: Why The Sudden Attention?
By Peter McCrorie on May 24, 2010
With DAC 2010 rapidly approaching, we can again expect that lots of EDA and IP vendors will use “mixed signal” somewhere in their company’s messaging.
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What you didn’t know about DFM for advanced node designs: “In-route” is insufficient
By Manoj Chacko on May 14, 2010
Recently, there has been a lot of buzz about addressing DFM issues during routing.
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  Virtuoso Custom IC Platform News
VIA’s Centaur Achieves Significant Benefits Using Cadence Virtuoso Space-Based Router at 65 Nanometers
RF Design Team Centaur Technology Improves Quality and Time Savings with Cadence Technology.
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Things You Didn’t Know About Virtuoso: It's Video Time!
By Stacy Whiteman on April 01, 2010
Just a quick post to let you know that there have recently been a whole truckload of videos added to the Cadence Online Support Video Library.
More»
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Cadence Delivers Extensive Support for TSMC Analog/Mixed-Signal Reference Flow 1.0 for 28nm Process
Collaboration Uses Market-Segment Leading Mixed-Signal Technologies to Support Comprehensive EDA360 Solution for Silicon Realization.
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The New, Simplified AMS Designer Virtuoso Use-Model
This article is meant for users of the AMS Designer Virtuoso Use-Model (AVUM).
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  Incisive Verification Platform News
EDA360 And The “Paperback Computer”
By Joseph Hupcey III on June 3, 2010
Have you ever heard an assertion that's so intriguing and farsighted that it sticks in your mind over a period of years; even decades?
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Cadence Kick-Starts UVM Adoption with Open-Source Reference Flow Contribution to UVM World
UVM Reference Flow Enables Users to Rapidly Learn and Apply the Universal Verification Methodology.
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Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.0
Enabling System To Silicon Realization, Flow Delivers Efficient Methodologies To Cut Time To Volume And Cost Of Development For TSMC’s Advanced Node Customers.
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EDA360 Is More Than Design IP Plus Software Drivers
By Tom Anderson on May 27, 2010
I checked my Linked-In messages the other day and saw a survey by Girish Patil with the provocative question “Is EDA360 the same experiment that Phoenix Technology tried a decade ago with the acquisition of Virtual Chips and Sand Micro?”
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  Allegro SPB Platform News
What's Good About AMS Simulator And Cursors? You’ll Need The SPB16.3
Release To See!
By Gerald “Jerry” Grzenia on June 1, 2010
With the SPB16.3 release of AMS Simulator, several new cursor enhancements are available
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What’s Good About Browsing For Power Pins in Capture? It's In SPB16.3!
By Gerald “Jerry” Grzenia on May 25, 2010
The SPB16.3 release of Allegro Design Entry CIS (Capture) now allows you to browse power pins in your design.
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