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Cadence Newsletter - Mayl 2010
Cadence India eNewsletter
Cadence Global Customer Support
Trainings & Workshops
More Information»
Digital IC

Logic Equivalence Checking with Encounter Conformal
EC v9.1
18 May 2010 - 19 May 2010
Bangalore, India

Signoff Power-Grid Analysis with Encounter Power
System v8.1
18 May 2010 - 19 May 2010
Bangalore, India

h4>CPF Covering Conformal Low Power- V9.1 Delivery Method: ILT
27 May 2010 - 27 May 2010
Bangalore, India

Floorplanning, Physical Synthesis, Place and Route (Hierarchical) v9.1
01 Jun 2010 - 01 Jun 2010
Bangalore, India

Custom IC

h4> Virtuoso Advance Spectre vMMSIM7.1
Delivery Method: ILT
25 May 2010 - 26 May 2010
Bangalore, India

Virtuoso Platform Update Training: Physical Design IC6.1 v6.1.3
02 Jun 2010 - 02 Jun 2010
Bangalore, India


Incisive Simulation of PSL Assertions v8.2
18 May 2010 - 18 May 2010
Bangalore, India

Specman Elite Basics for Verification Environment Users v8.1
24 May 2010 - 25 May 2010
Bangalore, India
May 2010 
EDA360 - What Is It and Why Should You Care?
  Encounter Digital IC Platform News
Hands Up, Anyone Believe That Toyota's Problems Are All Physical?
By Peter McCrorie on April 26, 2010
In the past number of weeks/months we have all seen how Toyota has struggled to manage perception around their "sudden acceleration" problems. More»
EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D
By Rahul Deokar on April 16, 2010
Every April the leading edge of the leading edge of semiconductor industry meet at the Electronic Design Process (EDP) Symposium to address design problems that make design more difficult than it should be. More»
  Virtuoso Custom IC Platform News
HiSilicon Adopts Cadence Mixed-Signal and Low-Power Technologies
Large Chinese Fabless IC Design Company Expands Collaboration with Cadence on Advanced Wireless and Networking Chip Designs. More»
LSI Adopts Broad Range of Cadence Mixed Signal Technologies
Cadence Technology to Drive LSI’s Custom IC and Mixed-Signal SoC Efforts. More»
Analog/Mixed Signal Routing Challenges in Sub- Nanometer Designs
By Girraj Khandelwal, Custom IC Technical Field Operations
The IC industry is facing several design and manufacturing/yield related challenges as process geometries continue to shrink. More»
  Incisive Verification Platform News

Cadence Contributes Technology to Boost Verification of Complex
Mixed-Signal Chips

Donated to the Accellera Standards Group, the Wreal Model Enables Faster and More Comprehensive Verification. More»
Cadence Debuts Verification Computing Platform, Accelerating Time and Improving Quality of System Development
New Unified, Scalable Verification Platform Increases Productivity of Design Teams, Supports Next-Generation SoC. More»

VIA’s Centaur Achieves Significant Benefits Using Cadence Virtuoso Space-Based Router at 65 Nanometers

Centaur Technology Improves Quality and Time Savings with Cadence Technology. More»
  Allegro SPB Platform News
What's Good About DEHDL Alignment? You’ve got it in the SPB16.3 Release!
By Gerald "Jerry" Grzenia on May 5, 2010
Schematic construction requires a lot of effort in placing components, wires and text/notes in such a way that the end schematic looks neatly organized. More»
What's Good About APD’s Super Smooth Routing? See for yourself in the SPB16.3 Release!
By Gerald "Jerry" Grzenia on April 29, 2010
When using the point-to-point routing in the packaging products (APD and SIP), customers spend a significant amount of their efforts to clean up the traces after routing. More»

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