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Cadence Newsletter - April 2010
Cadence India eNewsletter

Philips Streamlines Complex SoC Development Process Using Cadence Incisive Xtreme Verification System. More»
Trainings & Workshops
More Information»
Digital IC

Encounter RTL Compiler v9.1
20 Apr 2010 - 21 Apr 2010
Bangalore, India

Floorplanning, Physical Synthesis, Place and
Route (Flat) v9.1
03 May 2010 - 05 May 2010
Bangalore, India

Logic Equivalence Checking with Encounter
Conformal EC v9.1
12 Apr 2010 - 13 Apr 2010
Bangalore, India

Custom IC

Analog Modeling with Verilog-A v6.2
03 May 2010 - 05 May 2010
Bangalore, India

SKILL Programming for IC Layout Design v5.1.41
12 Apr 2010 - 13 Apr 2010
Bangalore, India


Specman Elite Advanced Verification v8.1
03 May 2010 - 05 May 2010
Bangalore, India

SystemC Language Fundamentals v8.2
12 Apr 2010 - 13 Apr 2010
Bangalore, India

SystemVerilog Advanced Verification using OVM v8.2
19 Apr 2010 - 23 Apr 2010
Bangalore, India

Silicon Package Board

Allegro AMS Simulator v16.2
10 May 2010 - 11 May 2010
Bangalore, India

April 2010 

Cadence Technology on Tour
  Encounter Digital IC Platform News
Renesas Cuts Design Time by Half on Large-Scale Consumer SoC by Using Cadence Encounter Technology
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, said today that Renesas Technology Corp. used the Cadence Encounter Digital Implementation (EDI) System and Encounter Conformal Low Power to layout a large-scale consumer system on chip (SoC) of over 8 million instances in one-half the time previously possible.  More»
IR Drop Analysis: It's Not Really Necessary, Is It?
By Peter McCrorie on April 5, 2010
I was recently asked by an engineering manager if running IR drop analysis was really necessary.  More»
  Virtuoso Custom IC Platform News
Rohde&Schwarz Achieves Higher Quality RFICs with Cadence Virtuoso Accelerated Parallel Simulator
RF Design Team Increases Simulation Depth Up to 16x and Minimizes Tapeout Risks.  More»
Things You Didn't Know About Virtuoso: It's Video Time!
By Stacy Whiteman on April 1, 2010
Just a quick post to let you know that there have recently been a whole truckload of videos added to the Cadence Online Support Video Library. More»
IC614 Update for Schematic and Layout
By Brajesh Heda on April 10, 2010
There are lots of basic enhancements have been done in IC614 release. More»
  Incisive Verification Platform News
When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?
By Team Specman on March 30, 2010
A famous expression in the software world is that you can only expect 10 good lines of production code per day.  More»
When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?
By Team Specman on April 6, 2010
In my last post I wrote some packet generation code to validate the claim that e code can be up to 3 times more compact vs. the equivalent functionality in System Verilog. More»
  Allegro SPB Platform News
Cadence Teams with AcAe to Accelerate Customer Transitions to Allegro PCB Products
AcAe Resources and Services Ease Customer Migrations from Legacy Technologies to Allegro PCB Design Tools and Other Cadence PCB Solutions.  More»
Cadence OrCAD PSpice Technology to be Used by STMicroelectronics to Help its Customers Evaluate Analog and Power ICs

OrCAD PSpice Platform Offers Robust Simulation Capabilities. More»

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