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Cadence India eNewsletter

IBM Accelerates Large-scale PCB System Design Using Unique Cadence Multi-style Design Entry Solution  More»
Trainings & Workshops
More Information»
Digital IC

Floorplanning, Physical Synthesis, Place and Route (Flat) v9.1
23 Mar 2010 - 25 Mar 2010,
Bangalore, India

Signoff Timing Analysis with Encounter Timing System v8.1
21 Dec 2010 - 23 Dec 2010,
Bangalore, India

Custom IC

Virtuoso XL Layout Editor v5.1.41
24 Mar 2010 - 26 Mar 2010,
Bangalore, India

SKILL Language Programming v5.1.41
05 Apr 2010 - 08 Apr 2010,
Bangalore, India


SystemVerilog Advanced Verification using OVM v8.2
15 Mar 2010 - 19 Mar 2010,
Bangalore, India

March 2010 
Cadence nominated for EDN Innovation Awards
  Encounter Digital IC Platform News
Cadence Customers and Partners Contribute to Success of New Digital Design Technology
New Encounter Digital Implementation System enables superior design productivity and quality  More»
Encounter How To: Writing To/Reading From a File With TCL
By Robert Dwyer on February 24, 2010
A couple weeks ago, there was a good thread in the Digital Implementation Forums about managing buffering on nets between IOs and registers. More»
  Virtuoso Custom IC Platform News
Library Variability Analysis using Cadence Litho Electrical Analyzer (LEA)
Brajesh Heda, Lead App. Engineer, Cadence Design Systems, India.
This eNewsLetter will explain methodology related to LEA library variability analysis  More»
Custom designers benefit from greater performance, capacity, and productivity with the latest Virtuoso release
For many customers, custom design is the most profitable part of the business–and the most challenging  More»
Things You Didn't Know About Virtuoso: IC 6.1.4 ADE Enhancements
By Stacy Whiteman on March 10, 2010
I'm not going to beat around the bush here. I could tell you about all the things that are new in ADE (Analog Design Environment) in IC 6.1.4.More»
  Incisive Verification Platform News
Chipsbank Adopts Cadence Incisive Xtreme III System to Boost SoC Verification Performance
Cadence Technology Speeds Full-Chip Verification 500 Times More»
Why OOP Falls Short For Verification
By Team Specman on March 3, 2010
Last week at DVCon, frequent Team Specman guest blogger Matan Vax of R&D gave a paper on "Where OOP Falls Short of Verification Needs". More»
  Allegro SPB Platform News
What’s Good About Capture’s Auto-Wiring? You’ll Need The SPB16.3 Release to See!
By Gerald "Jerry" Grzenia on March 4, 2010
Just a brief post this week to highlight one of the new SPB16.3 features in Allegro Design Entry CIS. More»
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