Encounter Digital IC Platform News

Cadence Encounter Digital Implementation System 9.1 Addresses Industry Productivity Crisis for Complex System-on-Chip Design.

New Design Exploration, Integrated Signoff/DFM Analysis, Increased Performance and Capacity Drive Productivity Gains and Faster Time-to-Market for Multimillion Gate SoCs.More»

Austriamicrosystems Expands Reliance on Cadence Technology to Achieve Seamless Mixed-Signal SoC Designs.

Austriamicrosystems Has Extended Its Collaboration With Cadence by Selecting Encounter Digital Implementation System for Digital Designs. More»

  Virtuoso Custom IC Platform News

Renesas Adopts Cadence Virtuoso Technology for Mixed- Signal and Analog Design at its Global Design Centers.

Constraint-Driven Design and Verification Expected to Reduce Turnaround Time by 30%. More»

Custom Layout Migration and DFM Optimization using Virtuoso Layout Migrate (VLM)

In this competitive world, quality of product and time to market are essential for growth of any semiconductor company. More»

  Incisive Verification Platform News

Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric.

Company Cites 40% Reuse Leading to Lower Costs, Better Quality. More»

An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog.

By Tom Anderson on February 5, 2010.

In my last blog entry, I implored Accellera to release UVM 1.0 quickly, standardizing OVM 2.1 as is, with full backwards compatibility and without trying to cram overlapping functionaity from VMM into the base. More»

  Allegro SPB Platform News

What's Good About DEHDL Font Support? The Secret's in The SPB16.3 Release!

By Gerald "Jerry" Grzenia on February 4, 2010

Well - it's here! Native font support in Allegro Design Entry HDL (DEHDL)! This has been a often requested feature and is particularly important for our mil-aero customers. More»