Cadence India eNewsletter
Silicon Laboratories Improves Verification Speed and Product Quality Using Incisive Enterprise Simulator

Digital Mixed–Signal Option Makes Regressions Run Dramatically Faster More»
Trainings & Workshops
More Information»
Digital IC

Logic Equivalence Checking with Encounter Conformal EC-v7.1
18 Nov 2009 - 19 Nov 2009,
Bangalore, India

Encounter Test JumpStart to ATPG - v7.2
30 Nov 2009 - 30 Nov 2009,
Bangalore, India

Encounter RTL Compiler Advance course -v8.1
02 Dec 2009 - 03 Dec 2009,
Bangalore, India

Custom IC

Virtuoso Platform Update Training: Infrastructure ; Analog & Physical Design - vIC6.1.3
16 Nov 2009 - 18 Nov 2009,
Bangalore, India

SKILL Language Programming-v5.1.41
24 Nov 2009 - 27 Nov 2009,
Bangalore, India

SKILL Programming for IC Layout Design-v5.1.4126
30 Nov 2009 - 01 Dec 2009,
Bangalore, India


Incisive Comprehensive Coverage-v8.1
09 Nov 2009 - 09 Nov 2009,
Bangalore, India

Assertion-based Verification using PSL in the Incisive Formal Verifier
13 Nov 2009 - 13 Nov 2009,
Bangalore, India

Silicon Package Board

Allegro PCB SI Foundations-v16.2
16 Nov 2009 - 17 Nov 2009,
Bangalore, India

November 2009 
CDNLive! India 09 - Review
  Encounter Digital IC Platform News
Exar Selects Cadence as Mixed-Signal EDA Provider.
Breadth and Quality of Product Portfolio Key Drivers of Broadened Agreement. More»
Hitachi Achieves Test Compression Levels Four Years Ahead of Industry (ITRS) Roadmap by Leveraging Cadence OPMISR Compression Technology.
Encounter Test Solution with Hitachi HBIST Enables 1,100X Compression with over 99% AC fault coverage.  More»
  Virtuoso Custom IC Platform News
STARC and Cadence Collaborate to Develop Next–Generation Analog/Mixed–Signal Reference Flow.
Japanese Consortium and Cadence Will Develop Flow Using Cadence Virtuoso Technology as Its Foundation.  More»
Introducing Virtuoso Pcell IDE in IC 6.1.4
Mayank Kumar, Deepti Kamal & Vivek Astvansh - Cadence Design Systems
Debugging Parameterized Cells (Pcells) has historically been a manual task where you load the SKILL code in the CIW and instantiates a few configurations of the Pcell to verify correctness of the code. More»
Long Term Jitter Measurements.
The procedures described in this document are deliberately broad and generic. Your specific design might require procedures that are slightly different from those described here.  More»
  Incisive Verification Platform News
Cadence Introduces Incisive Enterprise Verifier, Delivering Dual Power of Formal Analysis and Simulation Engines.
New Integrated Solution Increases Return on Investment from Assertion-Based Verification and Eases Adoption for Design and Verification Engineers.  More»
Cadence Incisive Verification Management Solution Enables Fujitsu Microelectronics Solutions to Achieve Aggressive Verification Goals.
Simpler Verification Planning and Management Process with Automated Metric–Driven Flow Improve Productivity and Predictability  More»
  Allegro SPB Platform News
Cadence Leverages New Miniaturization Capabilities to Advance PCB Design Leadership.
Latest Release of Allegro and OrCAD PCB Software Boosts Productivity and Performance While Reducing Design Cycle Time. More»
IC Package Designers Boost Productivity with New Cadence Allegro SiP and IC Packaging Software.
New Software Release with Co–Design and Design Chain Enablement Technology Helps Engineers Shorten Design Cycles  More»