Cadence India eNewsletter
Constraint-Driven High-Density Interconnect (HDI) PCB Design Flow Helps NVIDIA Speed Products to Market More»
Trainings & Workshops
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Digital IC

Floorplanning, Physical Synthesis, Place and Route-V8.1
21 Oct 2009 - 23 Oct 2009,
Bangalore, India

Encounter RTL Compiler Basic Training -v8.1
23 Oct 2009 - 23 Oct 2009,
Bangalore, India

Custom IC

Virtuoso Platform Update Training: Infrastructure; Analog & Physical Design - vIC6.1.3
12 Oct 2009 - 14 Oct 2009,
Bangalore, India

Analog Modeling with Verilog-A-v6.2
26 Oct 2009 - 28 Oct 2009,
Bangalore, India

Virtuoso Spectre Circuit Simulator-vMMSIM6.0
04 Nov 2009 - 06 Nov 2009,
Bangalore, India


Incisive Unified Simulator
21 Oct 2009 - 22 Oct 2009,
Bangalore, India

Basic SystemVerilog for Design and Verification-V8.1
27 Oct 2009 - 28 Oct 2009,
Bangalore, India

SVA-Incisive Simulation of PSL Assertions-V8.2
04 Nov 2009 - 04 Nov 2009,
Bangalore, India

Silicon Package Board

Allegro PCB Editor Advanced Techniques-v16.01
26 Oct 2009 - 27 Oct 2009,
Bangalore, India

October 2009 
CDNLive! India 09 Registration Now Open!
  Encounter Digital IC Platform News
Cadence Extends Performance Leadership with Expanded Multi-Core Support.
Enhanced Engine Performance in Design, Verification, Custom, PCB and IC Packaging Broadens Cadence Multi-Core Support. More»
Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects.
By Kari Summers on August 28, 2009 
Have you ever gotten to signoff DRC and found that there was a small area where a filler cell did not get placed for some reason? More»
  Virtuoso Custom IC Platform News
EXT 8.1.2: What’s New
Product Version EXT 8.1.2 More»
Application Note: Using Ultrasim Power Analysis Option to Simulate Wasted and Capacitive Currents
This application note addresses how to use UltraSim’s power analysis options to simulate the wasted and capacitive currents consumed by a circuit.  More»
  Incisive Verification Platform News
Cadence Extends Its TLM-Driven Design and Verification Solution to Support Leading Embedded Software Environments.
Provides Unique OVM-based Hardware/Software Co-Verification with TLM Sub-System and Unified Hardware/Software Co-Debug Graphical User Interface. More»
Cadence Enables Early Validation of Next-Gen 4G/LTE Wireless Designs with Rohde & Schwarz T&M Solution.
New Solution Integrating Cadence Emulator with R&S Wideband Communication Tester Allows Engineers to Test Wireless Designs Much Earlier in Design Cycle. More»
  Allegro SPB Platform News
What’s Good About APD's Design Integrity Check? - It’s in SPB16.2!
By Gerald "Jerry" Grzenia on September 30, 2009 
The Cadence IC Packaging tools are complex, flexible tools that allow a designer freedom to create a package substrate layout in a myriad of ways. More»
What’s Good About Allegro’s Component Placement Changes? - More Features in SPB16.2!
By Gerald "Jerry" Grzenia on September 23, 2009.
In the SPB16.2 release of Allegro PCB Editor, there are two (2) new very helpful features (among the many others) that assist PCB designers with component placement - Component Alignment and Placement Replication. More»